Datasheet > CE71J4

CE71J4

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
富士通 - FUJITSU		/
页数	文件大小	规格书
4页	56K
描述
0.25um CMOS Technology

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数据手册

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CE71J4 数据手册

CE71 Series Embedded Array

Memory Macros

L-Series with 44µm Inline Pad Pitch and Au Bump

• SRAM Compiler: single and dual port (1 R/W, 1R), up to

72K bits per block, both BUS and PartialWrite

• ROM Compiler: up to 512K bits per block

• High-density single-port RAM 288K bits

• Register file (2R/W, 2R/2W), up to 4,608 bits

Frame

CE71L4

CE71L5

CE71L6

CE71L7

CE71L8

CE71L9

CE71LA

CE71LB

CE71LC

CE71LD

CE71LE

Total Gates

356K

Total Pads

304

Signals

264

304

360

428

504

476K

352

677K

420

1,034K

1,469K

1,976K

2,513K

3,001K

3,506K

4,050K

5,043K

520

620

720

Phase-Locked Loops

• Analog: up to 250 MHz (622 MHz under development)

812

888

960

I/Os

1,032

1,152

• 2.5V, 3.3V, and 5V tolerant

• Slew-rate controlled

• CMOS,TTL, PCML,T-LVTTL, LVDS, PCI, SSTL,

GTL+,AGP, USB

T-Series with 88µm Inline Pad Pitch and Wire Bonding

Frame

Total Gates

347K

Total Pads

144

Signals

128

156

178

192

206

220

248

264

312

360

264

CE71T2

CE71T3

CE71T4

CE71T5

CE71T6

CE71T7

CE71T8

CE71T9

CE71TA

CE71TB

CE71TC

CE71TD

CE71TE

CE71TG

SOC IP Cores

ARM 7TDMI Hard Macro

ARC 32-bit RISC

834/836 SPARClite Hard Macros

Oak DSP Hard Macro

10/100 MAC

524K

176

734K

208

845K

224

963K

240

1.110K

1.407K

1.559K

1.827K

2.088K

2.398K

3.040K

3.645K

5.152K

256

288

304

64/256 QAM

328

MPEG2 Decoder/Demultiplexer

8VSBTV Demodulator

AC-3 DolbyVoice Decoder

JPEG Encoder and Decoder

PCI–33/66 MHz, 32/64-bit cores

USB Host Controller/Device

352

376

424

464

552

I C

Mixed-Signal Macros

D/A Converters

• 10-bit: 1 MS/s, 1.5 MS/s,

30 MS/s, 50 MS/s,

IDE (ATA3) Host Controller

Smart Card I/F

IRDA I/R Interface

More IPs are being added

100 MS/s, 220 MS/s

• 8-bit: 200 KS/s, 1 MS/s, 50 MS/s

A/D Converters

ASIC Design Kit and EDA Support

• 12-bit: 1 MS/s

Verilog Logic Simulators from

Cadence, Synopsys, and Mentor

Verilog-XL, NC-Verilog,

VCS, Model-sim (Verilog)

• 10-bit: 1 MS/s, 20 MS/s, 40 MS/s

• 8-bit: 1 MS/s, 30 MS/s, 50 MS/s

• 6-bit: 100 MS/s, 500 MS/s

VHDL/VITAL Logic

Simulators from Synopsys,

Cadence, and Mentor

VSS, Model-sim (VHDL), V-System,

Leapfrog

Multiplier Compiler

• Multiplicand (m): 4 † m † 32

• Multiplier (n): 4 † n † 32 (even number only)

Synthesis, power, DFT, and

STA tools from Synopsys

Design Compiler, Design Power, Test

Compiler, PrimeTime, MOTIVE, and

Sunrise TestGen

Other EDA tools

Chrysalis Design Verifyer and

Sente Watt Watcher

Fujitsu Microelectronics, Inc.

123 4

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