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CD54HCT4046AF3A

更新时间： 2024-02-15 02:20:54
品牌 Logo 应用领域
德州仪器 - TI 信号电路锁相环或频率合成电路
页数 文件大小 规格书
28页 436K
描述
High-Speed CMOS Logic Phase-Locked Loop with VCO

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中文翻译

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CD54HCT4046AF3A 技术参数

生命周期：Active零件包装代码：DIP
包装说明：DIP-16针数：16
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：5.11Is Samacsys：N
模拟集成电路 - 其他类型：PHASE LOCKED LOOPJESD-30 代码：R-GDIP-T16
长度：19.56 mm功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified筛选级别：38535Q/M;38534H;883B
座面最大高度：4.57 mm子类别：PLL or Frequency Synthesis Circuits
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.92 mmBase Number Matches：1

CD54HCT4046AF3A 数据手册

 浏览型号CD54HCT4046AF3A的Datasheet PDF文件第1页浏览型号CD54HCT4046AF3A的Datasheet PDF文件第2页浏览型号CD54HCT4046AF3A的Datasheet PDF文件第3页浏览型号CD54HCT4046AF3A的Datasheet PDF文件第5页浏览型号CD54HCT4046AF3A的Datasheet PDF文件第6页浏览型号CD54HCT4046AF3A的Datasheet PDF文件第7页 
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A  
The frequency capture range (2f ) is defined as the  
C
frequency range of input signals on which the PLL will lock if  
V
V
V
=
(V /4π) (φSIG  
CC  
-
φCOMP )  
IN  
where  
DEMOUT  
DEMOUT  
DEMOUT  
IN  
is the demodulator output at pin 10;  
= V (via low-pass filter).  
PC2OUT  
it was initially out-of-lock. The frequency lock range (2f ) is  
L
defined as the frequency range of input signals on which the  
loop will stay locked if it was initially in lock. The capture  
range is smaller or equal to the lock range.  
The average output voltage from PC2, fed to the VCO via the  
low-pass filter and seen at the demodulator output at pin 10  
(V  
), is the resultant of the phase differences of  
DEMOUT  
With PC1, the capture range depends on the low-pass filter SIG and COMP as shown in Figure 4. Typical waveforms  
IN IN  
characteristics and can be made as large as the lock range. for the PC2 loop locked at f are shown in Figure 5.  
o
This configuration retains lock behavior even with very noisy  
V
CC  
input signals. Typical of this type of phase comparator is that  
it can lock to input frequencies close to the harmonics of the  
VCO center frequency.  
V
DEMOUT (AV)  
V
CC  
1/2 V  
CC  
V
DEMOUT (AV)  
1/2 V  
CC  
0
o
o
o
φDEMOUT  
-360  
0
360  
FIGURE 4. PHASE COMPARATOR 2: AVERAGE OUTPUT  
VOLTAGE vs INPUT PHASE DIFFERENCE:  
0
o
o
o
φDEMOUT  
0
90  
180  
V
= V  
DEMOUT  
PC2OUT  
= (V /4π) (φSIG - φCOMP );  
CC IN IN  
φ
= (φSIG - φCOMP )  
FIGURE 2. PHASE COMPARATOR 1: AVERAGE OUTPUT  
VOLTAGE vs INPUT PHASE DIFFERENCE:  
DEMOUT IN IN  
V
= V  
= (V /π) (φSIG  
= (φSIG - φCOMP  
IN  
-
)
IN  
DEMOUT  
PC1OUT  
DEMOUT  
CC  
IN  
φCOMP ); φ  
IN  
SIG  
IN  
COMP  
IN  
VCO  
OUT  
V
CC  
PC2  
OUT  
SIG  
GND  
IN  
HIGH IMPEDANCE OFF - STATE  
COMP  
IN  
VCO  
IN  
VCO  
OUT  
PCP  
OUT  
PC1  
OUT  
FIGURE 5. TYPICAL WAVEFORMS FOR PLL USING PHASE  
COMPARATOR 2, LOOP LOCKED AT f  
V
CC  
o
VCO  
IN  
GND  
When the frequencies of SIG and COMP are equal but  
IN IN  
FIGURE 3. TYPICAL WAVEFORMS FOR PLL USING PHASE  
the phase of SIG leads that of COMP , the p-type output  
IN IN  
COMPARATOR 1, LOOP LOCKED AT f  
o
driver at PC2  
is held “ON” for a time corresponding to  
OUT  
the phase difference (φ  
). When the phase of SIG  
DEMOUT  
lags that of COMP , the n-type driver is held “ON”.  
IN  
Phase Comparator 2 (PC2)  
IN  
When the frequency of SIG  
is higher than that of  
This is a positive edge-triggered phase and frequency  
detector. When the PLL is using this comparator, the loop  
is controlled by positive signal transitions and the duty  
IN  
COMP , the p-type output driver is held “ON” for most of  
IN  
the input signal cycle time, and for the remainder of the  
cycle both n- and p-type drivers are “OFF” (three-state). If  
the SIG frequency is lower than the COMP frequency,  
factors of SIG and COMP are not important. PC2  
IN IN  
comprises two D-type flip-flops, control-gating and a three-  
state output stage. The circuit functions as an up-down  
IN  
IN  
then it is the n-type driver that is held “ON” for most of the  
cycle. Subsequently, the voltage at the capacitor (C2) of  
counter (Figure 1) where SIG causes an up-count and  
IN  
the low-pass filter connected to PC2  
varies until the  
COMP  
a down-count. The transfer function of PC2,  
OUT  
signal and comparator inputs are equal in both phase and  
IN  
assuming ripple (f = f ) is suppressed, is:  
r
i
4
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中文翻译

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CD54HCT4046AF3A 替代型号

型号 品牌 替代类型 描述 数据表
CD74HCT4046AM TI

完全替代

 High-Speed CMOS Logic Phase-Locked Loop with VCO
CD74HCT4046AE TI

完全替代

 High-Speed CMOS Logic Phase-Locked Loop with VCO
CD74HC4046APWR TI

功能相似

 High-Speed CMOS Logic Phase-Locked Loop with VCO

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