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CD4068 PDF预览

CD4068

更新时间: 2024-02-28 18:35:09
品牌 Logo 应用领域
英特矽尔 - INTERSIL
页数 文件大小 规格书
8页 68K
描述
CMOS 8 Input NAND/AND Gate

CD4068 数据手册

 浏览型号CD4068的Datasheet PDF文件第2页浏览型号CD4068的Datasheet PDF文件第3页浏览型号CD4068的Datasheet PDF文件第4页浏览型号CD4068的Datasheet PDF文件第5页浏览型号CD4068的Datasheet PDF文件第6页浏览型号CD4068的Datasheet PDF文件第7页 
CD4068BMS  
CMOS 8 Input NAND/AND Gate  
December 1992  
Features  
Pinout  
CD4068BMS  
TOP VIEW  
• High Voltage Type (20V Rating)  
• Medium Speed Operation  
K = A · B · C · D · E · F · G · H  
1
2
3
4
5
6
7
14 VDD  
- TPHL, TPLH = 75ns (Typ.) at VDD = 10V  
A
B
13 J = A · B · C · D · E · F · G · H  
• Buffered Inputs and Outputs  
12 H  
11 G  
10 F  
• 5V, 10V and 15V Parametric Ratings  
• Standardized Symmetrical Output Characteristics  
• 100% Tested for Quiescent Current at 20V  
C
D
NC  
VSS  
9
8
E
• Maximum Input Current of 1µA at 18V Over Full Pack-  
NC  
age Temperature Range; 100nA at 18V and +25oC  
NC = NO CONNECTION  
• Noise Margin (Over Full Package/Temperature Range)  
- 1V at VDD = 5V  
- 2V at VDD = 10V  
Functional Diagram  
- 2.5V at VDD = 15V  
• Meets All Requirements of JEDEC Tentative Standard  
No. 13B, “Standard Specifications for Description of  
‘B’ Series CMOS Devices”  
2
3
4
A
B
C
D
1
5
K
J
Description  
13  
CD4068BMS NAND/AND gate provides the system designer  
with direct implementation of the positive logic 8 Input NAND and  
AND functions and supplements the existing family of CMOS  
gates.  
9
E
F
10  
11  
12  
J = A · B · C · D · E · F · G · H  
K = A · B · C · D · E · F · G · H  
G
H
The CD4068BMS is supplied in these 14 lead outline packages:  
VDD = 14  
Braze Seal DIP  
Frit Seal DIP  
H4H  
H1B  
VSS = 7  
6, 8 = NO CONNECTION  
Ceramic Flatpack H3W  
Logic Diagram  
A
B
2
3
C
D
E
F
4
5
13  
1
J
9
K
10  
11  
12  
G
H
FIGURE 1. LOGIC DIAGRAM  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 3320  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
7-985  

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