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CAT9883

更新时间： 2022-08-07 18:34:11

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CAT9883 数据手册

CAT9883C

PV_D: Clock Generator Power Supply.

internal clock generator and is synchronous with the internal

pixel sampling clock. When the sampling time is changed by

adjusting the PHASE register, the output timing is shifted as

well. The Data, DATACK, and HSOUT outputs are all moved,

so the timing relationship among the signals is maintained.

The most sensitive portion of the CAT9883C is the clock

generation circuitry. These pins provide power to the clock

PLL and help the user design for optimal performance. The

designer should provide quiet, noise-free power to these pins.

GND: Ground.

POWER SUPPLY

The ground return for all circuitry on-chip. It is recommended

that the CAT9883C be assembled on a single solid ground

plane, with careful attention given to ground current paths.

V_D: Main Power Supply.

These pins supply power to the main elements of the circuit.

They should be filtered and as quiet as possible.

SERIAL PORT (2-Wire)

SDA: Serial Port Data I/O.

SCL: Serial Port Data Clock.

V_DD: Digital Output Power Supply.

A large number of output pins (up to 25) switching at high

speed (up to 110 MHz) generates a lot of power supply

transients (noise). These supply pins are identified separately

from the VD pins so special care can be taken to minimize

output noise transferred into the sensitive analog circuitry. If

the CAT9883C is interfacing with lower voltage logic, _VDDmay

be connected to a lower supply voltage (as low as 2.5 V) for

compatibility.

A0: Serial Port Address Input 1.

For a full description of the 2-wire serial register and how it

works, refer to the 2-Wire Serial Control Port section.

The CAT logo is a registered trademark of Chip Advanced Technology

Aug-2007 Rev:1.0 7/23

1...4 5 678 9 10...23

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