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CAT33C804APITE13 PDF预览

CAT33C804APITE13

更新时间: 2024-01-09 06:18:00
品牌 Logo 应用领域
CATALYST 可编程只读存储器
页数 文件大小 规格书
14页 93K
描述
4K-Bit Secure Access Serial E2PROM

CAT33C804APITE13 数据手册

 浏览型号CAT33C804APITE13的Datasheet PDF文件第2页浏览型号CAT33C804APITE13的Datasheet PDF文件第3页浏览型号CAT33C804APITE13的Datasheet PDF文件第4页浏览型号CAT33C804APITE13的Datasheet PDF文件第5页浏览型号CAT33C804APITE13的Datasheet PDF文件第6页浏览型号CAT33C804APITE13的Datasheet PDF文件第7页 
Preliminary  
CAT33C804A  
4K-Bit Secure Access Serial E2PROM  
FEATURES  
Single 3V Supply  
100,000 Program/Erase Cycles  
Password READ/WRITE Protection: 1 to 8 Bytes  
Memory Pointer WRITE Protection  
Sequential READ Operation  
I/O Speed: 9600 Baud  
–Clock Frequency: 4.9152 MHz Xtal  
Low Power Consumption:  
–Active: 3 mA  
256 x 16 or 512 x 8 Selectable Serial Memory  
UART Compatible Asynchronous Protocol  
–Standby: 250 µA  
100 Year Data Retention  
Commercial, Industrial and Automotive  
Temperature Ranges  
DESCRIPTION  
The CAT33C804A is a 4K-bit Serial E2PROM that safe-  
guards stored data from unauthorized access by use of  
a user selectable (1 to 8 byte) access code and a  
movablememorypointer. Twooperatingmodesprovide  
unprotected and password-protected operation allow-  
ing the user to configure the device as anything from a  
ROM to a fully protected no-access memory. The  
CAT33C804A uses a UART compatible asynchronous  
protocol and has a Sequential Read feature where data  
can be sequentially clocked out of the memory array.  
The device is available in 8-pin DIP or 16-pin SOIC  
packages.  
PIN CONFIGURATION  
BLOCK DIAGRAM  
DIP Package (P)  
SOIC Package (J)  
V
1
2
3
4
8
7
6
5
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC  
CS  
CLK  
DI  
V
NC  
NC  
CS  
CLK  
DI  
NC  
NC  
V
CC  
GND  
PE  
64-BIT ACCESS CODE  
ERR  
GND  
&
CC  
CONTROL BLOCK  
DO  
PE  
DO  
ERR  
GND  
NC  
SERIAL  
CLK  
DO  
NC  
NC  
COMMUNI-  
CATION  
BLOCK  
PE  
CS  
DI  
4K-BIT EEPROM  
ARRAY  
NC  
PIN FUNCTIONS  
5074 FHD F01  
R/W  
ADDRESS  
Pin Name  
Function  
BUFFER  
DECODER  
INSTRUCTION  
REGISTER  
CS  
Chip Select  
DO(1)  
CLK  
DI(1)  
PE  
Serial Data Output  
Clock Input  
INSTRUCTION  
DECODER  
ADDRESS  
REGISTER  
ERR  
Serial Data Input  
Parity Enable  
STATUS  
REGISTER  
MEMORY  
POINTER  
ERR  
VCC  
GND  
Error Indication Pin  
+3V Power Supply  
Ground  
33C804 F02  
Note:  
(1) DI, DO may be tied together to form a common I/O.  
© 1998 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 25044-00 2/98  
1

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