Datasheet > CAT24C022PI-45TE13

CAT24C022PI-45TE13

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
CATALYST		监控控制器可编程只读存储器
页数	文件大小	规格书
12页	89K
描述
Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer

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Advanced

CAT24CXX1/XX2

FUNCTIONAL DESCRIPTION

STOP Condition

The CAT24CXXX supports the I²C Bus data transmis-

sion protocol. This Inter-Integrated Circuit Bus protocol

defines any device that sends data to the bus to be a

transmitter and any device receiving data to be a re-

ceiver. The transfer is controlled by the Master device

which generates the serial clock and all START and

STOP conditions for bus access. The CAT24CXXX

operates as a Slave device. Both the Master device and

Slave device can operate as either transmitter or re-

ceiver, but the Master device controls which mode is

activated.

A LOW to HIGH transition of SDA when SCL is HIGH

determinestheSTOPcondition.Alloperationsmustend

with a STOP condition.

DEVICE ADDRESSING

The Master begins a transmission by sending a START

condition. The Master sends the address of the particu-

larslavedeviceitisrequesting. Thefourmostsignificant

bits of the 8-bit slave address are fixed as 1010.

The next three bits (Fig. 6) define memory addressing.

For the 24C021/022, the three bits are don't care. For

the 24C041/042, the next two bits are don't care and the

third bit is the high order address bit. For the 24C081/

082, the next bit is don't care and the successive bits

define the higher order address bits. For the 24C161/

162 the three bits define higher order bits.

I²C BUS PROTOCOL

The features of the I²C bus protocol are defined as

follows:

(1) Data transfer may be initiated only when the bus is

not busy.

The last bit of the slave address specifies whether a

Read or Write operation is to be performed. When this

bitissetto1, aReadoperationisselected, andwhenset

to 0, a Write operation is selected.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any changes in

thedatalinewhiletheclocklineishighwillbeinterpreted

as a START or STOP condition.

After the Master sends a START condition and the slave

address byte, the CAT24CXXX monitors the bus and

responds with an acknowledge (on the SDA line) when

its address matches the transmitted slave address. The

CAT24CXXX then performs a Read or Write operation

depending on the state of the R/W bit.

START Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDAwhenSCLisHIGH. TheCAT24CXXXmonitorsthe

SDA and SCL lines and will not respond until this

condition is met.

Figure 5. Acknowledge Timing

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

START

ACKNOWLEDGE

Figure 6. Slave Address Bits

24C021/022

R/W

24C081/082

24C161/162

a8 R/W

24C041/042

a10 a9

a8 R/W

* 'X' Corresponds to Don't Care Bits (can be a zero or a one)

** a8, a9 and a10 correspond to the address of the memory array address word.

Doc. No. 25079-00 1/98 M-1

1...4 5 678 9 10...12

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CAT24C023J25TE13	CATALYST	Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog	获取价格
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