Datasheet > CAT24C022PA-30

CAT24C022PA-30

更新时间： 2023-04-15 00:00:00

品牌	Logo	应用领域
CATALYST		光电二极管
页数	文件大小	规格书
12页	71K
描述
Microprocessor Circuit, CMOS, PDIP8, PLASTIC, DIP-8

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CAT24C022PA-30 数据手册

CAT24CXX1/XX2

STOP Condition

FUNCTIONAL DESCRIPTION

TheCAT24CXXXsupportstheI²CBusdatatransmission

protocol.ThisInter-IntegratedCircuitBusprotocoldefines

any device that sends data to the bus to be a transmitter

and any device receiving data to be a receiver. The

transfer is controlled by the Master device which

generates the serial clock and all START and STOP

conditions for bus access. Both the Master device and

Slavedevicecanoperateaseithertransmitterorreceiver,

but the Master device controls which mode is activated.

A LOW to HIGH transition of SDA when SCL is HIGH

determinestheSTOPcondition.Alloperationsmustend

with a STOP condition.

DEVICE ADDRESSING

The Master begins a transmission by sending a START

condition.TheMastersendstheaddressoftheparticular

slave device it is requesting. The four most significant

bits of the 8-bit slave address are fixed as 1010.

I²C Bus Protocol

Thenextthreebits(Figure6)definememoryaddressing.

For the CAT24C021/022, the three bits don’t care. For

theCAT24C041/042,thenexttwobitsaredon’tcareand

the third bit is the high order address bit. For the

CAT24C081/082, the next bit is don’t care and the

successive bits define the higher order address bits. For

the CAT24C161/162 the three bits define higher order

bits.

The features of the I²C bus protocol are defined as

follows:

(1) Data transfer may be initiated only when the bus is

not busy.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any changes in

thedatalinewhiletheclocklineishighwillbeinterpreted

as a START or STOP condition.

The last bit of the slave address specifies whether a

ReadorWriteoperationistobeperformed.Whenthisbit

is set to 1, a Read operation is selected, and when set

to 0, a Write operation is selected.

START Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDA when SCL is HIGH. The CAT24CXX1 monitors the

SDA and SCL lines and will not respond until this

condition is met.

After the Master sends a START condition and the slave

address byte, the CAT24CXXX monitors the bus and

responds with an acknowledge (on the SDA line) when

its address matches the transmitted slave address. The

CAT24CXXX then performs a Read or Write operation

depending on the R/W bit.

Figure 5. Acknowledge Timing

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

START

ACKNOWLEDGE

Figure 6. Slave Address Bits

24C023

R/W

24C083

24C163

a8 R/W

24C043

a10 a9

a8 R/W

* 'X' Corresponds to Don't Care Bits (can be a zero or a one)

** a8, a9 and a10 correspond to the address of the memory array address word.

Doc No. 3000, Rev. A

1...4 5 678 9 10...12

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与CAT24C022PA-30相关器件

型号	品牌	获取价格	描述	数据表
CAT24C022PA-30TE13	CATALYST	获取价格	Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog
CAT24C022PA-42	CATALYST	获取价格	Microprocessor Circuit, CMOS, PDIP8, PLASTIC, DIP-8
CAT24C022PA-42TE13	CATALYST	获取价格	Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog
CAT24C022PA-45	CATALYST	获取价格	Microprocessor Circuit, CMOS, PDIP8, PLASTIC, DIP-8
CAT24C022PA-45TE13	CATALYST	获取价格	Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog
CAT24C022PI-25TE13	CATALYST	获取价格	Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog
CAT24C022PI-28TE13	CATALYST	获取价格	Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog
CAT24C022PI-30	CATALYST	获取价格	Microprocessor Circuit, CMOS, PDIP8, PLASTIC, DIP-8
CAT24C022PI-30TE13	CATALYST	获取价格	Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog
CAT24C022PI-42	CATALYST	获取价格	Microprocessor Circuit, CMOS, PDIP8, PLASTIC, DIP-8

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