CAT24CXX1/XX2
STOP Condition
FUNCTIONAL DESCRIPTION
TheCAT24CXXXsupportstheI2CBusdatatransmission
protocol.ThisInter-IntegratedCircuitBusprotocoldefines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. The
transfer is controlled by the Master device which
generates the serial clock and all START and STOP
conditions for bus access. Both the Master device and
Slavedevicecanoperateaseithertransmitterorreceiver,
but the Master device controls which mode is activated.
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition.TheMastersendstheaddressoftheparticular
slave device it is requesting. The four most significant
bits of the 8-bit slave address are fixed as 1010.
I2C Bus Protocol
Thenextthreebits(Figure6)definememoryaddressing.
For the CAT24C021/022, the three bits don’t care. For
theCAT24C041/042,thenexttwobitsaredon’tcareand
the third bit is the high order address bit. For the
CAT24C081/082, the next bit is don’t care and the
successive bits define the higher order address bits. For
the CAT24C161/162 the three bits define higher order
bits.
The features of the I2C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes in
thedatalinewhiletheclocklineishighwillbeinterpreted
as a START or STOP condition.
The last bit of the slave address specifies whether a
ReadorWriteoperationistobeperformed.Whenthisbit
is set to 1, a Read operation is selected, and when set
to 0, a Write operation is selected.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24CXX1 monitors the
SDA and SCL lines and will not respond until this
condition is met.
After the Master sends a START condition and the slave
address byte, the CAT24CXXX monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24CXXX then performs a Read or Write operation
depending on the R/W bit.
Figure 5. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 6. Slave Address Bits
24C023
1
0
1
0
X
X
X
X
X
R/W
24C083
24C163
1
1
0
0
1
1
0
0
X
a9
a8 R/W
a8 R/W
24C043
a10 a9
1
0
1
0
a8 R/W
* 'X' Corresponds to Don't Care Bits (can be a zero or a one)
** a8, a9 and a10 correspond to the address of the memory array address word.
Doc No. 3000, Rev. A
7