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CAT24C021PI-45 PDF预览

CAT24C021PI-45

更新时间: 2024-01-18 04:17:29
品牌 Logo 应用领域
CATALYST 光电二极管外围集成电路
页数 文件大小 规格书
12页 71K
描述
Microprocessor Circuit, CMOS, PDIP8, PLASTIC, DIP-8

CAT24C021PI-45 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP,
针数:8Reach Compliance Code:unknown
HTS代码:8542.31.00.01风险等级:5.92
JESD-30 代码:R-PDIP-T8JESD-609代码:e0
长度:9.27 mm端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
认证状态:Not Qualified座面最大高度:4.57 mm
最大供电电压:6 V最小供电电压:2.7 V
标称供电电压:5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUIT
Base Number Matches:1

CAT24C021PI-45 数据手册

 浏览型号CAT24C021PI-45的Datasheet PDF文件第4页浏览型号CAT24C021PI-45的Datasheet PDF文件第5页浏览型号CAT24C021PI-45的Datasheet PDF文件第6页浏览型号CAT24C021PI-45的Datasheet PDF文件第8页浏览型号CAT24C021PI-45的Datasheet PDF文件第9页浏览型号CAT24C021PI-45的Datasheet PDF文件第10页 
CAT24CXX1/XX2  
STOP Condition  
FUNCTIONAL DESCRIPTION  
TheCAT24CXXXsupportstheI2CBusdatatransmission  
protocol.ThisInter-IntegratedCircuitBusprotocoldefines  
any device that sends data to the bus to be a transmitter  
and any device receiving data to be a receiver. The  
transfer is controlled by the Master device which  
generates the serial clock and all START and STOP  
conditions for bus access. Both the Master device and  
Slavedevicecanoperateaseithertransmitterorreceiver,  
but the Master device controls which mode is activated.  
A LOW to HIGH transition of SDA when SCL is HIGH  
determinestheSTOPcondition.Alloperationsmustend  
with a STOP condition.  
DEVICE ADDRESSING  
The Master begins a transmission by sending a START  
condition.TheMastersendstheaddressoftheparticular  
slave device it is requesting. The four most significant  
bits of the 8-bit slave address are fixed as 1010.  
I2C Bus Protocol  
Thenextthreebits(Figure6)definememoryaddressing.  
For the CAT24C021/022, the three bits don’t care. For  
theCAT24C041/042,thenexttwobitsaredon’tcareand  
the third bit is the high order address bit. For the  
CAT24C081/082, the next bit is don’t care and the  
successive bits define the higher order address bits. For  
the CAT24C161/162 the three bits define higher order  
bits.  
The features of the I2C bus protocol are defined as  
follows:  
(1) Data transfer may be initiated only when the bus is  
not busy.  
(2) During a data transfer, the data line must remain  
stable whenever the clock line is high. Any changes in  
thedatalinewhiletheclocklineishighwillbeinterpreted  
as a START or STOP condition.  
The last bit of the slave address specifies whether a  
ReadorWriteoperationistobeperformed.Whenthisbit  
is set to 1, a Read operation is selected, and when set  
to 0, a Write operation is selected.  
START Condition  
The START Condition precedes all commands to the  
device, and is defined as a HIGH to LOW transition of  
SDA when SCL is HIGH. The CAT24CXX1 monitors the  
SDA and SCL lines and will not respond until this  
condition is met.  
After the Master sends a START condition and the slave  
address byte, the CAT24CXXX monitors the bus and  
responds with an acknowledge (on the SDA line) when  
its address matches the transmitted slave address. The  
CAT24CXXX then performs a Read or Write operation  
depending on the R/W bit.  
Figure 5. Acknowledge Timing  
SCL FROM  
MASTER  
1
8
9
DATA OUTPUT  
FROM TRANSMITTER  
DATA OUTPUT  
FROM RECEIVER  
START  
ACKNOWLEDGE  
Figure 6. Slave Address Bits  
24C023  
1
0
1
0
X
X
X
X
X
R/W  
24C083  
24C163  
1
1
0
0
1
1
0
0
X
a9  
a8 R/W  
a8 R/W  
24C043  
a10 a9  
1
0
1
0
a8 R/W  
* 'X' Corresponds to Don't Care Bits (can be a zero or a one)  
** a8, a9 and a10 correspond to the address of the memory array address word.  
Doc No. 3000, Rev. A  
7

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