Datasheet > CAT1163JI-25

CAT1163JI-25

更新时间： 2023-01-03 08:22:37

品牌	Logo	应用领域
CATALYST		光电二极管
页数	文件大小	规格书
12页	69K
描述
SPECIALTY MICROPROCESSOR CIRCUIT, PDSO8, SOIC-8

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数据手册

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CAT1163JI-25 数据手册

CAT1163

CAPACITANCE

T = 25˚C, f = 1.0 MHz, V

= 5V

Symbol Test

Max

Units

Conditions

V_I/O= 0V

V_IN= 0V

(1)

C_I/O

Input/Output Capacitance (SDA)

Input Capacitance (SCL)

(1)

C_IN

AC CHARACTERISTICS

V_CC=2.7V to 6.0V unless otherwise specified.

Output Load is 1 TTL Gate and 100pF.

_CC= 2.7V - 6V

V_CC= 4.5V - 5.5V

SYMBOL PARAMETER

Min

Max

100

200

Min

Max

400

200

Units

kHz

F_SCL

T_I⁽¹⁾

Clock Frequency

Noise Suppresion Time

Constant at SCL, SDA Inputs

SLC Low to SDA Data Out

and ACK Out

t_AA

3.5

µs

(1)

t_BUF

Time the Bus Must be Free Before

a New Transmission Can Start

4.7

1.2

t_HD:STA

t_LOW

Start Condition Hold Time

Clock Low Period

0.6

1.2

0.6

µs

4.7

t_HIGH

Clock High Period

t_SU:STA

Start Condition Setup Time

(for a Repeated Start Condition)

4.7

t_HD:DAT

t_SU:DAT

Data in Hold Time

µs

Data in Setup Time

(1)

t_R

SDA and SCL Rise Time

SDA and SCL Fall Time

Stop Condition Setup Time

Data Out Hold Time

0.3

(1)

t_F

300

t_SU:STO

t_DH

0.6

100

(1)(2)

POWER-UP TIMING

Symbol Parameter

Max

Units

t_PUR

t_PUW

Power-up to Read Operation

Power-up to Write Operation

WRITE CYCLE LIMITS

Symbol Parameter

Min

Typ

Max

Units

t_WR

Write Cycle Time

The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the

write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.

NOTE:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2)

and t

are the delays required from the time V is stable until the specific operation can be initiated.

PUR

PUW

Doc No. 3003, Rev. C

1 234 5 6 7...12

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