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CAP018DG

更新时间： 2024-02-05 08:15:02
品牌 Logo 应用领域
帕沃英蒂格盛 - POWERINT 光电二极管
页数 文件大小 规格书
8页 604K
描述
Zero Loss Automatic X Capacitor Discharge IC

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CAP018DG 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：SOIC包装说明：SOP,
针数：8Reach Compliance Code：compliant
HTS代码：8542.39.00.01Factory Lead Time：14 weeks
风险等级：5.58模拟集成电路 - 其他类型：ANALOG CIRCUIT
JESD-30 代码：R-PDSO-G8JESD-609代码：e3
长度：4.9 mm湿度敏感等级：1
功能数量：1端子数量：8
最高工作温度：105 °C最低工作温度：-10 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.75 mm表面贴装：YES
温度等级：OTHER端子面层：MATTE TIN
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：3.9 mmBase Number Matches：1

CAP018DG 数据手册

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CAPZero Family  
R1  
D1  
MOVPOS1  
MOVPOS2  
Other EMI  
Filter  
Components  
CEXT  
AC  
X Capacitor1  
X Capacitor2  
D2  
CAPZero  
R2  
PI-6600-110711  
Figure 3. Placement Options of MOV and CEXT  
.
If the measured peak Drain voltage exceeds 950 V, an external  
1 kV ceramic capacitor of value up to 47 pF can also be placed  
between D1 and D2 terminals to attenuate the voltage applied  
between the CAPZero terminals during surge. This optional  
external capacitor placement is shown as CEꢁT in Figure 3. It  
should be noted that use of an external capacitor in this way will  
increase power consumption slightly due to the CEꢁT charge/  
discharge currents flowing in R1 and R2 while AC is connected.  
A CEꢁT value of 33 pF will add approximately 0.5 mW at 230 VAC,  
50 Hz.  
Key Application Considerations  
Breakdown Voltage Selection  
Figure 3 illustrates possible system configurations influencing  
the choice of CAPZero breakdown voltage. The system  
configuration variables include the placement of the system  
MOV and ꢁ capacitor(s) as well as the differential surge voltage  
specifications of the application.  
As shown in Table 1, each device in the CAPZero family has a  
825 V or 1000 V option. For applications where the system  
MOV is placed in position 1 (MOVPOS1 in Figure 3), the 825 V  
option will typically provide adequate voltage withstand for  
surge requirements up to 3 kV or more. The 1 kV CAPZero  
would be recommended for higher surge requirements or if  
additional voltage margin is required.  
PCB Layout and External Resistor Selection  
Figure 4 shows a typical PCB layout configuration for CAPZero.  
The external resistors in this case are divided into two separate  
surface mount resistors to distribute loss under fault conditions  
– for example where a short-circuit exists between CAPZero  
terminals D1 and D2. R1 and R2 values are selected according  
to Table 1.  
For MOV placement that is not directly across the ꢁ Capacitor1  
(for example MOVPOS2 in Figure 3) the 1000 V CAPZero devices  
can be used up to a surge specification of 1.5 kV. For differential  
surge voltage specifications of >1.5 kV it is recommended that  
the MOV is always placed in the location shown in Figure 3 as  
Under a fault condition where CAPZero terminals D1 and D2 are  
shorted together, each resistor will dissipate a power that can  
be calculated from the applied AC voltage and the R1 and R2  
values. For example in an application using CAP004 or CAP014,  
R1=R2=390 kW. If CAPZero is shorted out at 265 VAC R1 and  
R2 will each dissipate 45 mW.  
MOVPOS1  
.
It is always recommended that the peak voltage between  
terminals D1 and D2 of CAPZero is measured during surge  
tests in the final system. Measurements of peak voltage across  
CAPZero during surge tests should be made with oscilloscope  
probes having appropriate voltage rating and using an isolated  
supply to the oscilloscope to avoid ground currents influencing  
measurement results. When making such measurements, it is  
recommended that 50 V engineering margin is allowed below  
the breakdown voltage specification (for example 950 V with the  
1000 V CAPZero).  
Resistors R1 and R2 should also be rated for 50ꢀ of the system  
input voltage again to allow for the short-circuitry of CAPZero  
D1 to D2 pins during single point fault testing.  
If lower dissipation or lower voltage across each resistor is  
required during fault tests, the total external resistance can be  
divided into more discrete resistors, however the total resistance  
must be equal to that specified in Table 1.  
3
www.powerint.com  
Rev. D 11/11  
12345678

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