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C9851BT

更新时间： 2024-01-28 20:00:22
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 晶体时钟发生器微控制器和处理器外围集成电路光电二极管服务器
页数 文件大小 规格书
14页 125K
描述
Clock Generator for Pentium III Server and Workstation Applications

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C9851BT 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP-48
针数：48Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.92JESD-30 代码：R-PDSO-G48
JESD-609代码：e0长度：12.5 mm
端子数量：48最高工作温度：70 °C
最低工作温度：最大输出时钟频率：200 MHz
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP48,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V主时钟/晶体标称频率：14.318 MHz
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Clock Generators最大压摆率：30 mA
最大供电电压：3.465 V最小供电电压：3.135 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：6.1 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches：1

C9851BT 数据手册

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PRELIMINARY  
C9851  
Clock Generator for Pentium III Server and Workstation Applications  
AC Parameters (VDDI = VDD = VDDR = VDDL = VDDM = VDDC = 3.3V ±5%, TA = 0°C to +70°C)  
133 MHz Host  
100 MHz Host  
Symbol  
Parameter  
CPU[(1:6), (1:6)#] period -  
Min  
7.35  
175  
-
-
-
Max  
7.65  
450  
150  
100  
150  
Voh+0.2  
-0.2  
55%Voh  
55  
Min  
9.85  
175  
-
-
-
Max  
10.2  
450  
150  
100  
150  
Voh+0.2  
-0.2  
55%Voh  
55  
Units  
Notes  
1, 2  
2, 3  
2, 4, 5  
2, 4, 5  
2, 4, 5  
2,10  
2, 10  
2, 4  
TPeriod  
Tr / Tf  
TSKEW1  
TSKEW2  
TCCJ  
nS  
pS  
pS  
pS  
pS  
V
V
V
%
CPU[(1:6), (1:6)#] rise and fall times  
skew from any CPU pair to any CPU pair  
skew from package to package  
CPU[(1:6), (1:6)#] Cycle to Cycle Jitter  
CPU[(1:6), (1:6)#] Overshoot  
CPU[(1:6), (1:6)#] Undershoot  
CPU(1:6) to CPU(1:6)# crossover point  
Duty Cycle  
Vover  
Vunder  
Vcrossover  
Tduty  
45%Voh  
45  
45%Voh  
45  
2, 4  
TPeriod  
THIGH  
TLOW  
Tr / Tf  
TSKEW  
TCCJ  
3V(MREF, MREF_B) period  
3V(MREF, MREF_B) high time  
3V(MREF, MREF_B) low time  
3V(MREF, MREF_B) rise and fall times  
3VMREF to 3VMREF_B skew  
3V(MREF, MREF_B) Cycle to Cycle Jitter  
Duty Cycle  
15.0  
5.25  
5.05  
0.4  
-
15.3  
-
-
1.6  
250  
250  
55  
20.0  
7.5  
7.3  
0.4  
-
20.4  
-
-
1.6  
250  
250  
55  
nS  
nS  
nS  
nS  
pS  
pS  
%
4, 5  
2, 6  
2, 7  
2, 3  
2, 4, 5, 11  
2, 4, 5  
2, 4  
-
45  
-
45  
Tduty  
TPeriod  
THIGH  
TLOW  
Tr / Tf  
TCCJ  
3V66 period  
3V66 high time  
3V66 low time  
3V66 rise and fall times  
3V66 Cycle to Cycle Jitter  
Duty Cycle  
15.0  
5.25  
5.05  
0.5  
-
16.0  
-
-
2.0  
300  
55  
15.0  
5.25  
5.05  
0.5  
-
15.2  
-
-
2.0  
300  
55  
nS  
nS  
nS  
nS  
pS  
%
1, 2, 4  
2,6  
2, 7  
2, 3  
2, 4, 5  
2, 4  
Tduty  
45  
45  
TPeriod  
Tr / Tf  
TCCJ  
REF period  
69.8413  
1.0  
-
71.0  
4.0  
1000  
55  
69.8413  
1.0  
-
71.0  
4.0  
1000  
55  
nS  
nS  
pS  
%
1, 2, 4  
2, 3  
2, 4  
REF rise and fall times  
REFCycle to Cycle Jitter  
Duty Cycle  
Tduty  
45  
45  
2, 4  
tpZL, tpZH  
tpLZ, tpZH  
tstable  
Output enable delay (all outputs)  
Output disable delay (all outputs)  
All clock Stabilization from power-up  
1.0  
1.0  
10.0  
10.0  
3
1.0  
1.0  
10.0  
10.0  
3
nS  
nS  
mS  
9
9
Group Limits and Parameters (applicable to all settings: Sel133/100# = x) continued  
Note 1: This parameter is measured at the crossing points of the differential signals, and acquired as an average over 1uS duration, with a crystal  
center frequency of 14.31818MHz  
Note 2: All outputs loaded as per table 2 below.  
Note 3: Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and at 20% and 80% for  
CPU[(1:6), (1:6)#] signals. (see Figs.7A & 7B)  
Note 4: Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals and at crossing points for CPU clocks (see Figs.7A  
& 7B).  
Note 5: This measurement is applicable with Spread ON or Spread OFF.  
Note 6: Probes are placed on the pins, and measurements are acquired at 2.4V (see Figs. 7A & 7B)  
Note 7: Probes are placed on the pins, and measurements are acquired at 0.4V. (see Figs. 7A & 7B)  
Note 9: As this function is available through SEL(A,B), therefore, the time specified is guaranteed by design.  
Note 10: Determined as a fraction of 2*(Trp-Trn) / (Trp+Trn) where Trp is a rising edge and Trn is an intersecting falling edge.  
Note 11: 3VMref and 3VMref_b are 180 degrees out of phase, therefore, the skew is measured between the rising edge of one and the falling edge  
of the other.  
Cypress Semiconductor Corporation  
525 Los Coches St.  
Document#: 38-07068 Rev. **  
05/04/2001  
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571  
http://www.cypress.com  
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