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C9819ATB

更新时间： 2024-01-11 18:48:36
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 光电二极管外围集成电路
页数 文件大小 规格书
17页 198K
描述
Processor Specific Clock Generator, CMOS, PDSO48, TSSOP-48

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C9819ATB 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP,针数：48
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.8
JESD-30 代码：R-PDSO-G48JESD-609代码：e0
长度：12.5 mm端子数量：48
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
认证状态：Not Qualified座面最大高度：1.2 mm
表面贴装：YES技术：CMOS
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
宽度：6.1 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：1

C9819ATB 数据手册

 浏览型号C9819ATB的Datasheet PDF文件第1页浏览型号C9819ATB的Datasheet PDF文件第3页浏览型号C9819ATB的Datasheet PDF文件第4页浏览型号C9819ATB的Datasheet PDF文件第5页浏览型号C9819ATB的Datasheet PDF文件第6页浏览型号C9819ATB的Datasheet PDF文件第7页 
+/+…when timing is critical  
C9819  
133 MHz I2C Clock Generator for Mobile Pentium®III / Rambus Systems  
Preliminary  
Pin Description  
PIN No.  
Pin Name  
PWR  
VDD  
VDD  
TYPE  
Description  
2
3
Buffered outputs of the signal applied at Xin, typically 14.318MHz  
This is a Power-on Bi-directional pin. (see app. note page 3 for  
strapping). At power-up this pin is an input FE0 for selecting the  
frequency extension percentage as in table 5, p. 9.  
REF0  
FE0 / REF1  
PU  
When the supply reaches the rail, this pin becomes REF1, a  
buffered output of the signal applied at Xin, typically 14.318MHz  
This is a Power-on Bi-directional pin. (see app. note page 3 for  
strapping). At power-up this pin is an input FE1 for selecting the  
frequency extension percentage as in table 5, p. 9.  
4
VDD  
PU  
FE1 / REF2  
When the supply reaches the rail, this pin becomes REF2, a buffered  
output of the signal applied at Xin, typically 14.318MHz  
Crystal Buffer input pin. Connects to a crystal, or a Can Oscillator.  
Serves as input clock TCLK, in Test mode.  
Crystal Buffer output pin. Connects to a crystal only. When a Can  
Oscillator is used or in Test mode, this pin is kept unconnected.  
3.3 V PCI clock outputs. These signals are synchronous to CPU  
clocks. When PCI_STP# is low, all except PCI_F synchronously  
stopped in a low state.  
6
7
VDD  
VDD  
VDD  
XIN  
XOUT  
11,12,14,15,  
17,18,20,21  
PCI(_F,0:6)  
23  
24  
VDD  
VDD  
PU  
PU  
When this pin is asserted low, the device is in Low Power State and  
all outputs are low and internal circuitry are shutoff.  
Input for frequency selection (see table1, page1).  
PWRDN#  
SEL133/100  
#
26  
28  
VDD  
VDD  
3.3 V Fixed 48 Mhz USB clock output.  
When this pin is asserted low, CPU0 is synchronously shutdown in a  
low state.  
48MHz  
CPU_stp#  
PU  
PU  
PU  
PU  
29  
30  
31  
VDD  
VDD  
VDD  
When this pin is asserted low, only PCI(0:6) are synchronously  
shutdown in a low state. PCI_F is not effected by this signal.  
Serial clock input pin. Conforms to the Philips I2C 100KHz  
Specification.  
Serial data input pin. Conforms to the Philips I2C specification of a  
Slave Receiver device. This pin is an input when receiving data. It is  
an open drain output when acknowledging. See I2C function  
description,p.6.  
PCI_stp#  
SCLK  
SDATA  
33,34,36  
VDD  
3.3 V Fixed 66.6Mhz Hub-link clock outputs. Synchronous to CPU  
clocks.  
3V66 (0:2)  
38  
43  
VDDC  
VDDC/2  
2.5 V Host bus clock output. Programmable per Table1, page1.  
2.5 V DRCG clock output. Half CPU frequency and synchronous to  
CPU clock.  
CPU  
CPU/2  
45,47  
VDDI  
2.5 V APIC clock outputs. Fixed at 16.67MHz and synchronous to  
CPU clock.  
IOAPIC(0,1)  
PU = Internal 250K Pull-up  
INTERNATIONAL MICROCIRCUITS, INC 525 LOS COCHES ST.  
MILPITAS, CA 95035, USA TEL: 408-263-6300 FAX 408-263-6571  
Rev 1.0  
11/1/1999  
Page 2 of 17  
http://www.imicorp.com  
1234567...17

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