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BD99010EFV-M

更新时间: 2024-01-30 01:26:21
品牌 Logo 应用领域
罗姆 - ROHM /
页数 文件大小 规格书
31页 1054K
描述
Simple Light Load Mode

BD99010EFV-M 数据手册

 浏览型号BD99010EFV-M的Datasheet PDF文件第23页浏览型号BD99010EFV-M的Datasheet PDF文件第24页浏览型号BD99010EFV-M的Datasheet PDF文件第25页浏览型号BD99010EFV-M的Datasheet PDF文件第27页浏览型号BD99010EFV-M的Datasheet PDF文件第28页浏览型号BD99010EFV-M的Datasheet PDF文件第29页 
Daattaasshheeeett  
BD99010EFV-M, BD99011EFV-M  
11. Testing on application boards  
The IC needs to be discharged after each test process as, while using the application board for testing, connecting a  
capacitor to a low-impedance pin may cause stress to the IC. As a protection from static electricity, ensure that the  
assembly setup is grounded and take sufficient caution with transportation and storage. Also, make sure to turn off  
the power supply when connecting and disconnecting the inspection equipment.  
12. GND wiring pattern  
When both a small-signal GND and a high current GND are present, single-point grounding (at the set standard point)  
is recommended. This in order to separate the small-signal and high current patterns and to ensure that voltage  
changes stemming from the wiring resistance and high current do not cause any voltage change in the small-signal  
GND. Similarly, care must be taken to avoid wiring pattern fluctuations in any connected external component GND.  
13. This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them  
isolated. P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a  
parasitic diode or transistor. Relations between each potential may form as shown in the example below, where a  
resistor and transistor are connected to a pin:  
o
With the resistor, when GNDPin A, and with the transistor (NPN), when GNDPin B:  
The P-N junction operates as a parasitic diode.  
o
With the transistor (NPN), when GNDPin B:  
The P-N junction operates as a parasitic transistor by interacting with the N layers of elements in proximity  
to the parasitic diode described above.  
Parasitic diodes inevitably occur in the structure of the IC. Their operation can result in mutual interference between  
circuits and can cause malfunctions and, in turn, physical damage to or destruction of the chip. Therefore do not  
employ any method in which parasitic diodes can operate such as applying a voltage to an input pin that is lower than  
the (P substrate) GND.  
Figure 48.  
14.  
REG PIN  
REG is output that supplies the internal circuit. We do not recommend using REG for any other purpose.  
www.rohm.com  
© 2013 ROHM Co., Ltd. All rights reserved.  
TSZ2211115001  
TSZ02201-0W1W0AL00030-1-2  
07.Jul.2014 Rev.003  
26/28  

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