Datasheet > AX88780_07

AX88780_07

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
亚信 - ASIX		控制器 PC 以太网局域网（LAN）标准
页数	文件大小	规格书
55页	454K
描述
High-Performance Non-PCI Single-Chip 32-bit 10/100M Fast Ethernet Controller

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AX88780_07 数据手册

AX88780

1.0 Introduction

1.1 General Description

AX88780 supports full-duplex or half-duplex operation at 10/100 Mbps speed with auto-negotiation or manual setting.

The AX88780 has two built-in synchronous SRAMs for buffering packet. The one is 32K bytes for receiving packets

from Ethernet; the other is 8K-bytes for transmitting packets from host system to Ethernet. The AX88780 also has 256

bytes built-in configuration registers. For software programming, the total address space used in AX88780 is 64K bytes in

32-bit mode and at least (8K + 8) bytes in 16-bit mode.

Because AX88780 is a SRAM-like device, AX88780 could be treated as a SRAM device and be attached to SRAM

controller of system. Therefore, system can execute DMA cycles to gain the highest performance. AX88780 needs 2 clock

sources, one is HCLK and another one is XTLP. The HCLK clock can be from the host system clock or from a stand-along

OSC, and the XTLP/XTLN clock is 25Mhz for internal PHY.

1.2 AX88780 Block Diagram

Figure 1: AX88780 block diagram

ASIX ELECTRONICS CORPORATION

1...4 5 678 9 10...55

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