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ATF22V10C_08

更新时间： 2022-12-27 23:41:45

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ATF22V10C_08 数据手册

ATF22V10C(Q)

4.7

Power-up Reset

The registers in the ATF22V10Cs are designed to reset during power-up. At a point delayed

slightly from V_CCcrossing V_RST, all registers will be reset to the low state. The output state will

depend on the polarity of the output buffer.

This feature is critical for state machine initialization. However, due to the asynchronous nature

of reset and the uncertainty of how V_CCactually rises in the system, the following conditions are

required:

1. The V_CCrise must be monotonic, and starts below 0.7V,

2. After reset occurs, all input and feedback setup times must be met before driving the

clock pin high, and

3. The clock must remain stable during t_PR

Figure 4-1. Power-up Reset Timing

POWER

REGISTERED

OUTPUTS

CLOCK

4.8

Preload of Registered Outputs

The ATF22V10C’s registers are provided with circuitry to allow loading of each register with

either a high or a low. This feature will simplify testing since any state can be forced into the reg-

isters to control test sequencing. A JEDEC file with preload is generated when a source file with

vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automati-

cally by most of the approved programmers after the programming.

5. Electronic Signature Word

There are 64 bits of programmable memory that are always available to the user, even if the

device is secured. These bits can be used for user-specific data.

6. Security Fuse Usage

A single fuse is provided to prevent unauthorized copying of the ATF22V10C fuse patterns.

Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature

remains accessible.

The security fuse should be programmed last, as its effect is immediate.

0735S–PLD–8/08

1...4 5 678 9 10...22

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