Datasheet > 可编程逻辑 > 可编程逻辑器件> ATF20V8B-10SI

ATF20V8B-10SI

更新时间： 2024-02-02 11:38:58

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
17页	761K
描述
High- Performance EE PLD

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技术参数
数据手册

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ATF20V8B-10SI 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	TSSOP	包装说明：	TSSOP,
针数：	24	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.5
最大时钟频率：	68 MHz	JESD-30 代码：	R-PDSO-G24
JESD-609代码：	e3	长度：	7.8 mm
湿度敏感等级：	2	专用输入次数：	12
I/O 线路数量：	8	端子数量：	24
最高工作温度：	70 °C	最低工作温度：
组织：	12 DEDICATED INPUTS, 8 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	可编程逻辑类型：	FLASH PLD
传播延迟：	10 ns	认证状态：	Not Qualified
座面最大高度：	1.2 mm	最大供电电压：	5.25 V
最小供电电压：	4.75 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
宽度：	4.4 mm	Base Number Matches：	1

ATF20V8B-10SI 数据手册

Input and I/O Pull-Ups

All ATF20V8B family members have internal input and I/O

pull-up resistors. Therefore, whenever inputs or I/Os are

not being driven externally, they will float to V_CC. This

ensures that all logic array inputs are at known states.

These are relatively weak active pull-ups that can easily be

overdriven by TTL-compatible drivers (see input and I/O

diagrams below).

Input Diagram

I/O Diagram

Functional Logic Diagram Description

The Logic Option and Functional Diagrams describe the

ATF20V8B architecture. Eight configurable macrocells can

be configured as a registered output, combinatorial I/O,

combinatorial output, or dedicated input.

subsets can be found in each of the configuration modes

described in the following pages. The user can download

the listed subset device JEDEC programming file to the

PLD programmer, and the ATF20V8B can be configured to

act like the chosen device. Check with your programmer

manufacturer for this capability.

The ATF20V8B can be configured in one of three different

modes. Each mode makes the ATF20V8B look like a dif-

ferent device. Most PLD compilers can choose the right

mode automatically. The user can also force the selection

by supplying the compiler with a mode selection. The deter-

mining factors would be the usage of register versus com-

binatorial outputs and dedicated outputs versus outputs

with output enable control.

Unused product terms are automatically disabled by the

compiler to decrease power consumption. A Security

Fuse, when programmed, protects the content of the

ATF20V8B. Eight bytes (64 fuses) of User Signature are

accessible to the user for purposes such as storing project

name, part number, revision, or date. The User Signature

is accessible regardless of the state of the Security Fuse.

The ATF20V8B universal architecture can be programmed

to emulate many 24-pin PAL devices. These architectural

ATF20V8B

1...3 4 567 8 9...17

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与ATF20V8B-10SI相关器件

型号	品牌	描述	获取价格	数据表
ATF20V8B-10XC	ATMEL	High- Performance EE PLD	获取价格
ATF20V8B-10XI	ATMEL	High- Performance EE PLD	获取价格
ATF20V8B-15GC	ETC	Electrically-Erasable PLD	获取价格
ATF20V8B-15GI	ATMEL	Flash PLD, 15ns, PAL-Type, CMOS, CDIP24, 0.300 INCH, CERDIP-24	获取价格
ATF20V8B-15GM	ETC	Electrically-Erasable PLD	获取价格
ATF20V8B-15GM/883	ETC	Electrically-Erasable PLD	获取价格

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