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ATF1500ABV-15JC PDF预览

ATF1500ABV-15JC

更新时间： 2024-01-30 06:46:47
品牌 Logo 应用领域
爱特美尔 - ATMEL /
页数 文件大小 规格书
12页 296K
描述
High- Performance EE PLD

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中文翻译

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ATF1500ABV-15JC 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：LCC包装说明：QCCJ,
针数：44Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.61
最大时钟频率：52.6 MHzJESD-30 代码：S-PQCC-J44
JESD-609代码：e3长度：16.5862 mm
湿度敏感等级：2专用输入次数：
I/O 线路数量：32端子数量：44
最高工作温度：85 °C最低工作温度：-40 °C
组织：0 DEDICATED INPUTS, 32 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：245可编程逻辑类型：FLASH PLD
传播延迟：15 ns认证状态：Not Qualified
座面最大高度：4.57 mm最大供电电压：5.5 V
最小供电电压：2.7 V标称供电电压：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：16.5862 mm

ATF1500ABV-15JC 数据手册

 浏览型号ATF1500ABV-15JC的Datasheet PDF文件第6页浏览型号ATF1500ABV-15JC的Datasheet PDF文件第7页浏览型号ATF1500ABV-15JC的Datasheet PDF文件第8页浏览型号ATF1500ABV-15JC的Datasheet PDF文件第9页浏览型号ATF1500ABV-15JC的Datasheet PDF文件第11页浏览型号ATF1500ABV-15JC的Datasheet PDF文件第12页 
Power Up Reset  
The ATF1500ABV’s registers are designed to reset during  
power up. At a point delayed slightly from VCC crossing  
VRST, all registers will be reset to the low state. As a result,  
the registered output state will always be low on power-up.  
This feature is critical for state machine initialization. How-  
ever, due to the asynchronous nature of reset and the  
uncertainty of how VCC actually rises in the system, the fol-  
lowing conditions are required:  
1. The VCC rise must be monotonic, from below .7  
volts.  
2. Signals from which clocks are derived must remain  
stable during TPR.  
Parameter  
Description  
Typ  
Max  
Units  
Power-Up  
Reset Time  
TPR  
2
10  
µs  
3. After TPR occurs, all input and feedback setup times  
must be met before driving the clock signal high.  
Power-Up  
Reset  
Voltage  
VRST  
2.2  
2.7  
V
Power Down Mode  
The ATF1500ABV includes an optional pin controlled  
power down feature. When this mode is enabled, the PD  
pin acts as the power down pin. When the PD pin is high,  
the device supply current is reduced to less than 10 µA.  
During power down, all output data and internal logic states  
are latched and held. Therefore, all registered and combi-  
natorial output data remain valid. Any outputs which were  
in a HI-Z state at the onset of power down will remain at HI-  
Z. During power down, all input signals except the power  
down pin are blocked. Input and I/O hold latches remain  
active to insure that pins do not float to indeterminate lev-  
els, further reducing system power. The power down pin  
feature is enabled in the logic design file. Designs using the  
power down pin may not use the PD pin logic array input.  
However, all other PD pin macrocell resources may still be  
used, including the buried feedback and foldback product  
term array inputs.  
Output Slew Rate Control  
Each ATF1500ABV macrocell contains a configuration bit  
for each I/O to control its output slew rate. This allows  
selected data paths to operate at maximum throughput  
while reducing system noise from outputs that are not  
speed-critical. Outputs default to slow edges, and may be  
individually set to fast in the design file. Output transition  
times for outputs configured as “slow” have a tSSO delay  
adder.  
Security Fuse Usage  
A single fuse is provided to prevent unauthorized copying  
of the ATF1500ABV fuse patterns. Once programmed, fuse  
verify and preload are prohibited. However, the 160-bit  
User Signature remains accessible.  
The security fuse should be programmed last, as its effect  
is immediate.  
Register Preload  
The ATF1500ABV’s registers are provided with circuitry to  
allow loading of each register with either a high or a low.  
This feature will simplify testing since any state can be  
forced into the registers to control test sequencing. A  
JEDEC file with preload is generated when a source file  
with preload vectors is compiled. Once downloaded, the  
JEDEC file preload sequence will be done automatically  
when vectors are run by any approved programmers. The  
preload mode is enabled by raising an input pin to a high  
voltage level. Contact Atmel PLD Applications for PRE-  
LOAD pin assignments, timing and voltage requirements.  
ATF1500ABV/L  
10  
1...789101112

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