ATA6832
2. Pin Configuration
Figure 2-1. Pinning QFN24
18 17 16 15 14 13
OUT3S
OUT3F
CS
1
2
3
4
5
6
12 OUT2F
11 VS2
10 VS1
DI
9
8
7
VCC
GND
DO
CLK
PWM
Table 2-1.
Pin Description
Pin
Symbol
Function
Used only for final testing, to be connected to OUT3F
1
OUT3S
Half-bridge output 3; formed by internally connecting power MOS high-side switch 3 and low-side switch 3
with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and
open load
2
OUT3F
Chip select input; 5V CMOS logic level input with internal pull-up;
low = serial communication is enabled, high = disabled
3
4
CS
DI
Serial data input; 5V CMOS logic level input with internal pull-down; receives serial data from the control
device; DI expects a 16-bit control word with LSB transferred first
Serial clock input; 5V CMOS logic level input with internal pull-down;
controls serial data input interface and internal shift register (fmax = 2 MHz)
5
6
CLK
PWM
PWM input; 5V CMOS logic level input with internal pull-down
Serial data output; 5V CMOS logic-level tri-state output for output (status) register data; sends 16-bit status
information to the microcontroller (LSB transferred first); output will remain tri-stated unless device is
selected by CS = low; this allows several ICs to operate on only one data-output line
7
DO
8
9
GND
VCC
VS1
VS2
Ground
Logic supply voltage (5V)
10
11
Power supply for output stages OUT1 and OUT2; internal supply
Power supply for output stages OUT2 and OUT3; internal supply
Half-bridge output 2; formed by internally connected power MOS high-side switch 2 and low-side switch 2
with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and
open load
12
OUT2F
13
14
OUT2S
PGND2
Used only for final testing, to be connected to OUT2F
Power ground OUT2
Half-bridge output 1; formed by internally connected power MOS high-side switch 1 and low-side switch 1
with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and
open load
15
OUT1F
16
17
18
OUT1S
PGND1
PGND3
Used only for final testing, to be connected to OUT1F
Power ground OUT1
Power ground OUT3
3
4951D–AUTO–08/09