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ATA6612P-PLQW PDF预览

ATA6612P-PLQW

更新时间: 2024-02-08 23:22:47
品牌 Logo 应用领域
爱特美尔 - ATMEL 稳压器微控制器和处理器外围集成电路异步传输模式ATM时钟
页数 文件大小 规格书
364页 5753K
描述
Microcontroller with LIN Transceiver, 5V Regulator and Watchdog

ATA6612P-PLQW 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFN包装说明:HVQCCN, LCC48,.27SQ,20
针数:48Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.31.00.01
风险等级:5.51Is Samacsys:N
具有ADC:YES其他特性:ALSO OPERATES AT 2.7V AT 8 MHZ
地址总线宽度:位大小:8
CPU系列:AVR RISC最大时钟频率:16 MHz
DAC 通道:NODMA 通道:NO
外部数据总线宽度:JESD-30 代码:S-XQCC-N48
长度:7 mmI/O 线路数量:23
端子数量:48最高工作温度:125 °C
最低工作温度:-40 °CPWM 通道:YES
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC48,.27SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE电源:5/27 V
认证状态:Not QualifiedRAM(字节):1024
ROM(单词):8192ROM可编程性:FLASH
座面最大高度:1 mm速度:16 MHz
子类别:Microcontrollers最大压摆率:53 mA
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD宽度:7 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLER, RISCBase Number Matches:1

ATA6612P-PLQW 数据手册

 浏览型号ATA6612P-PLQW的Datasheet PDF文件第4页浏览型号ATA6612P-PLQW的Datasheet PDF文件第5页浏览型号ATA6612P-PLQW的Datasheet PDF文件第6页浏览型号ATA6612P-PLQW的Datasheet PDF文件第8页浏览型号ATA6612P-PLQW的Datasheet PDF文件第9页浏览型号ATA6612P-PLQW的Datasheet PDF文件第10页 
ATA6612/ATA6613  
3.3  
Functional Description  
3.3.1  
Physical Layer Compatibility  
Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer),  
all nodes with a LIN physical layer according to revision 2.0 can be mixed with LIN physical layer  
nodes, which, according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3), are without  
any restrictions.  
3.3.2  
Supply Pin (VS)  
The LIN operating voltage is VS = 5V to 27V. An undervoltage detection is implemented to dis-  
able data transmission if VS falls below VSth < 4V in order to avoid false bus messages. After  
switching on VS, the IC starts in Fail-safe Mode, and the voltage regulator is switched on (i.e.,  
output capability).  
The supply current is typically 10 µA in Sleep Mode and 57 µA in Silent Mode.  
3.3.3  
3.3.4  
Ground Pin (GND)  
The IC is neutral on the LIN pin in the event of GND disconnection. It is able to handle a ground  
shift up to 11.5% of VS. The mandatory system ground is pin 5.  
Voltage Regulator Output Pin (VCC)  
The internal voltage regulator is capable of driving loads with up to 50 mA. It is able to supply the  
microcontroller and other ICs on the PCB and is protected against overloads by means of cur-  
rent limitation and overtemperature shut-down. Furthermore, the output voltage is monitored  
and will cause a reset signal at the NRES output pin if it drops below a defined threshold Vthun  
.
To boost up the maximum load current, an external NPN transistor may be used, with its base  
connected to the VCC pin and its emitter connected to PVCC.  
3.3.5  
3.3.6  
Voltage Regulator Sense Pin (PVCC)  
The PVCC is the sense input pin of the voltage regulator. For normal applications (i.e., when  
only using the internal output transistor), this pin is connected to the VCC pin. If an external  
boosting transistor is used, the PVCC pin must be connected to the output of this transistor, i.e.,  
its emitter terminal.  
Bus Pin (LIN)  
A low-side driver with internal current limitation and thermal shutdown and an internal pull-up  
resistor compliant with the LIN 2.0 specification are implemented. The allowed voltage range is  
between –27V and +40V. Reverse currents from the LIN bus to VS are suppressed, even in the  
event of GND shifts or battery disconnection. LIN receiver thresholds are compatible with the  
LIN protocol specification. The fall time from recessive to dominant bus state and the rise time  
from dominant to recessive bus state are slope controlled.  
7
9111E–AUTO–07/08  

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