Datasheet > ATA5577M1330C-DDB

ATA5577M1330C-DDB

更新时间： 2024-01-10 12:11:09

品牌	Logo	应用领域
爱特美尔 - ATMEL		电信电信集成电路
页数	文件大小	规格书
8页	137K
描述
Telecom Circuit

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技术参数
数据手册

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ATA5577M1330C-DDB 技术参数

生命周期：	Transferred	包装说明：	, DIE OR CHIP
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8523.59.00.00	风险等级：	5.11
JESD-30 代码：	R-XUUC-N	功能数量：	1
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装等效代码：	DIE OR CHIP
封装形状：	RECTANGULAR	封装形式：	UNCASED CHIP
认证状态：	Not Qualified	子类别：	Other Telecom ICs
表面贴装：	NO	电信集成电路类型：	TELECOM CIRCUIT
温度等级：	INDUSTRIAL	端子形式：	NO LEAD
端子位置：	UPPER	Base Number Matches：	1

ATA5577M1330C-DDB 数据手册

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ATA5577

4.1

Analog Front End (AFE)

The AFE includes all circuits that are directly connected to the coil terminals. It generates the

IC's power supply and handles the bi-directional data communication with the reader. It consists

of the following blocks:

• Rectifier to generate a DC supply voltage from the AC coil voltage

• Clock extractor

• Switchable load between Coil 1 and Coil 2 for data transmission from the tag to the reader

• Field-gap detector for data transmission from the base station to the tag

• ESD-protection circuitry

4.2

4.3

Data-rate Generator

The data rate is binary programmable to operate at any even-numbered data rate between RF/2

and RF/128 or to any of the fixed Basic mode data rates (RF/8, RF/16, RF/32, RF/40, RF/50,

RF/64, RF/100 and RF/128).

Write Decoder

The write decoder detects the write gaps and verifies the validity of the data stream according to

the Atmel e555x downlink protocol (pulse interval encoding).

4.4

4.5

HV Generator

DC Supply

This on-chip charge pump circuit generates the high voltage required to program the EEPROM.

Power is externally supplied to the IDIC via the two coil connections. The IC rectifies and regu-

lates this RF source and uses it to generate its supply voltage.

4.6

Power-On Reset (POR)

The power-on reset circuit blocks the voltage supply to the IDIC until an acceptable voltage

threshold has been reached.

4.7

4.8

Clock Extraction

The clock extraction circuit uses the external RF signal as its internal clock source.

Controller

The control logic module executes the following functions:

• Load mode register with configuration data from EEPROM block 0 after power-on and during

reading

• Load option register with the settings for the analog front end stored in EEPROM page 1

block 3 after power-on and during reading

• Control all EEPROM memory read/write access and data protection

• Handles the downlink command decoding detecting protocol violations and error conditions

4967DS–RFID–10/08

1 234 5 6 7 8

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