Datasheet > AT86RF230

AT86RF230

更新时间： 2024-01-01 15:11:54

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
50页	423K
描述
ZigBee/IEEE 802.15.4-Transceiver

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AT86RF230 技术参数

生命周期：	Active	包装说明：	HVQCCN,
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.79	JESD-30 代码：	S-XQCC-N32
长度：	5 mm	功能数量：	1
端子数量：	32	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	座面最大高度：	1 mm
标称供电电压：	3 V	表面贴装：	YES
技术：	CMOS	电信集成电路类型：	INTERFACE CIRCUIT
温度等级：	INDUSTRIAL	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	5 mm	Base Number Matches：	1

AT86RF230 数据手册

AT86RF230

2. General Circuit Description

Analog Domain

TX power

control

Digital Domain

DCLK

XOSC

DVREG

AVREG

BATMON

FTN

IRQ

TX Data

Frequency

Synthesis

SEL

TX BBP

MISO

RFP

RFN

Control Logic/

Configuration

Registers

SPI

Slave

Interface

SCLK

MOSI

TRX Data

Buffer

LNA

PPF

BPF

Limiter

AGC

ADC

RX BBP

CLKM

SLP_TR

RSTN

RSSI

Figure 2-1.

Block Diagram of AT86RF230

This single-chip RF transceiver provides a complete radio interface between the antenna and the micro-controller.

It comprises the analog radio part, digital demodulation including time and frequency synchronization and data

buffering. The number of external components is minimized so that only the antenna, the crystal and four

decoupling capacitors are required. The bidirectional differential antenna pins are used in common for RX and TX,

so no external antenna switch is needed.

The transceiver block diagram is shown in Figure 2-1. The receiver path is based on a low-IF topology. The

channel filter consists of three single side-band active RC resonators forming a 2 MHz band-pass filter with a

Butterworth characteristic centered at 2 MHz. Two 1^st-order high-pass filters were added to the signal path to

achieve capacitive coupling at the single side-band filter (SSBF) output to suppress DC offset and integrator

feedback at the limiter amplifier. The 3-stage limiter amplifier provides sufficient gain to overcome the DC offset of

the succeeding single channel ADC and generates a digital RSSI signal with 3 dB granularity. The low-IF signal is

sampled at 16 MHz with 1-bit resolution and applied to the digital signal processing part.

Direct VCO modulation is used to generate the transmit signal. The modulation scheme is offset-QPSK (O-QPSK)

with half-sine pulse shaping and 32-length block coding (spreading). This is equivalent to minimum shift keying

(MSK) when transforming the spreading code sequences appropriately. The modulation signal is applied to both

the VCO and the fractional-N PLL to ensure the coherent phase modulation required for demodulation as an O-

QPSK signal. The frequency-modulated LO signal is fed to the power amplifier.

Two on-chip low-dropout voltage regulators provide the analog and digital 1.8V supply. The SPI interface and the

control registers will retain their settings in SLEEP mode when the regulators are turned off. The RX and TX signal

processing paths are highly integrated and optimized for low power consumption.

5131A-ZIGB-06/14/06

1 2 3 456 7 8...50

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