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AT83C24-TISUM

更新时间： 2024-01-30 15:58:18

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
42页	726K
描述
Smart Card Reader Interface with Power Management

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技术参数
数据手册

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AT83C24-TISUM 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	SOP, SOP28,.56	Reach Compliance Code：	compliant
风险等级：	5.08	JESD-30 代码：	R-PDSO-G28
JESD-609代码：	e3	湿度敏感等级：	3
端子数量：	28	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP28,.56
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
电源：	3/5 V	认证状态：	Not Qualified
子类别：	Other Microprocessor ICs	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT
Base Number Matches：	1

AT83C24-TISUM 数据手册

Operational Modes

TWI Bus Control

The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire

bus, made up of one clock line and one data line with speeds of up to 400 Kbits per sec-

ond, based on a byte-oriented transfer format.

The TWI-bus interface can be used:

–

To configure the AT83C24

To select the operating mode of the card: 1.8V, 3V or 5V

To configure the automatic activation sequence

To start or stop sessions (activation and de-activation sequences)

To initiate a warm reset

To control the clock to the card in active mode

To control the clock to the card in stand-by mode (stop LOW, stop HIGH or

running)

–

To enter or leave the card stand-by or power-down modes

To select the interface (connection to the host I/O / C4/ C8)

To request the status (card present or not, over-current and out of range

supply voltage occurrence)

–

To drive and monitor the card contacts by software

To accurately measure the ATR delay when automatic activation is used

TWI Commands

Frame Structure

The structure of the TWI bus data frames is made of one or a series of write and read

commands completed by STOP.

Write commands to the AT83C24 have the structure:

ADDRESS BYTE + COMMAND BYTE + DATA BYTE(S)

Read commands to the AT83C24 have the structure:

ADDRESS BYTE + DATA BYTE(S)

The ADDRESS BYTE is sampled on A2/CK, A1/RST, A0/3V after each reset

(hard/soft/general call) but A2/CK, A1/RST, A0/3V can be used for transparent mode

after the reset.

Figure 1. Data transfer on TWI bus

acknowledgement

from slave

SDA

SCL

Adresse byte

command

and/or data

start condition

stop condition

AT83C24

4234E–SCR–09/04

1...3 4 567 8 9...42

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