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AT706S08 PDF预览

AT706S08

更新时间: 2022-11-25 11:23:03
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POSEICO /
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4页 48K
描述
PHASE CONTROL THYRISTOR

AT706S08 数据手册

 浏览型号AT706S08的Datasheet PDF文件第2页浏览型号AT706S08的Datasheet PDF文件第3页浏览型号AT706S08的Datasheet PDF文件第4页 
Via N. Lorenzi 8 - I 16152 GENOVA - ITALY  
Tel. int. +39/(0)10 6556549 - (0)10 6556488  
Fax Int. +39/(0)10 6442510  
Ansaldo Trasporti s.p.a.  
Unita' Semiconduttori  
ANSALDO  
Tx 270318 ANSUSE I -  
PHASE CONTROL THYRISTOR AT706  
Repetitive voltage up to  
Mean on-state current  
800 V  
4305 A  
70 kA  
Surge current  
FINAL SPECIFICATION  
feb 97 - ISSUE : 02  
Tj  
[°C]  
Symbol  
Characteristic  
Conditions  
Value  
Unit  
BLOCKING  
V RRM  
V RSM  
V DRM  
I RRM  
I DRM  
Repetitive peak reverse voltage  
Non-repetitive peak reverse voltage  
Repetitive peak off-state voltage  
Repetitive peak reverse current  
Repetitive peak off-state current  
125  
125  
125  
125  
125  
800  
900  
800  
200  
200  
V
V
V
V=VRRM  
V=VDRM  
mA  
mA  
CONDUCTING  
I T (AV)  
I T (AV)  
I TSM  
I² t  
Mean on-state current  
Mean on-state current  
Surge on-state current  
I² t  
180° sin, 50 Hz, Th=55°C, double side cooled  
180° sin, 50 Hz, Tc=85°C, double side cooled  
sine wave, 10 ms  
4305  
3335  
70  
A
A
125  
kA  
without reverse voltage  
24500 x1E3  
1.5  
A²s  
V
V T  
On-state voltage  
On-state current = 10000 A  
25  
V T(TO)  
r T  
Threshold voltage  
On-state slope resistance  
125  
0.84  
V
125 0.060  
mohm  
SWITCHING  
di/dt  
dv/dt  
td  
Critical rate of rise of on-state current, min. From 75% VDRM up to 3100 A, gate 10V 5ohm 125  
320  
500  
3
A/µs  
V/µs  
µs  
Critical rate of rise of off-state voltage, min. Linear ramp up to 70% of VDRM  
125  
25  
Gate controlled delay time, typical  
Circuit commutated turn-off time, typical  
Reverse recovery charge  
VD=100V, gate source 10V, 10 ohm , tr=.5 µs  
tq  
dV/dt = 20 V/µs linear up to 75% VDRM  
di/dt=-20 A/µs, I= 2050 A  
VR= 50 V  
160  
µs  
Q rr  
I rr  
I H  
125  
µC  
A
Peak reverse recovery current  
Holding current, typical  
VD=5V, gate open circuit  
VD=5V, tp=30µs  
25  
25  
300  
700  
mA  
mA  
I L  
Latching current, typical  
GATE  
V GT  
Gate trigger voltage  
VD=5V  
25  
25  
3.5  
250  
0.25  
30  
V
mA  
V
I GT  
Gate trigger current  
VD=5V  
V GD  
V FGM  
Non-trigger gate voltage, min.  
Peak gate voltage (forward)  
Peak gate current  
VD=VDRM  
125  
V
I
FGM  
10  
A
V RGM  
P GM  
P G  
Peak gate voltage (reverse)  
Peak gate power dissipation  
Average gate power dissipation  
5
V
Pulse width 100 µs  
150  
2
W
W
MOUNTING  
R th(j-h)  
Thermal impedance, DC  
Thermal impedance  
Junction to heatsink, double side cooled  
Case to heatsink, double side cooled  
11  
2
°C/kW  
°C/kW  
R th(c-h)  
T j  
F
Operating junction temperature  
Mounting force  
-30 / 125  
40.0 / 50.0  
1700  
°C  
kN  
g
Mass  
ORDERING INFORMATION : AT706 S 08  
VDRM&VRRM/100  
standard specification  

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