Datasheet > AT708LTS08

AT708LTS08

更新时间： 2022-02-26 12:35:54

品牌	Logo	应用领域
POSEICO		/
页数	文件大小	规格书
4页	156K
描述
PHASE CONTROL THYRISTOR

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数据手册

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AT708LTS08 数据手册

POSEICO SPA

Via Pillea 42-44, 16153 Genova - ITALY

Tel. + 39 010 8599400 - Fax + 39 010 8682006

Sales Office:

Tel. + 39 010 8599400 - sales@poseico.com

PHASE CONTROL THYRISTOR

AT708LT

Repetitive voltage up to

Mean forward current

Surge current

800 V

5439 A

70 kA

FINAL SPECIFICATION

Feb. 17 - Issue: 3

[°C]

Symbol

Characteristic

Conditions

Value

Unit

BLOCKING

V RRM

V RSM

V DRM

Repetitive peak reverse voltage

Non-repetitive peak reverse voltage

Repetitive peak off-state voltage

Repetitive peak reverse current

Repetitive peak off-state current

140

800

900

800

200

RRM

DRM

V=VRRM

V=VDRM

CONDUCTING

T (AV)

TSM

Mean forward current

180° sin, 50 Hz, Th=55°C, double side cooled

180° sin, 50 Hz, Tc=85°C, double side cooled

5439

4751

Mean forward current

Surge forward current

I² t

Sine wave, 10 ms

without reverse voltage

140

x 10³

I² t

24500

1,44

A²s

V T

On-state voltage

Threshold voltage

On-state slope resistance

On-state current =

10000 A

140

V T(TO)

0,84

0,060

mohm

SWITCHING

From 75% VDRM up to 3900 A; gate 10V, 5W

di/dt

Critical rate of rise of on-state current, min.

Critical rate of rise of off-state voltage, min.

Gate controlled delay time, typical

Circuit commutated turn-off time, typical

Reverse recovery charge

140

320

500

A/µs

V/µs

µs

dv/dt

Linear ramp up to 70% of VDRM

VD=100V; gate source 10V, 10W , tr=.5 µs

dv/dt = 20 V/µs linear up to 75% VDRM

di/dt = -20 A/µs, I= 2600 A

VR= 50 V

160

µs

Q rr

140

µC

Peak reverse recovery current

Holding current, typical

VD=5V, gate open circuit

VD=5V, tp=30µs

300

Latching current, typical

1000

GATE

V GT

Gate trigger voltage

VD=5V

3,50

250

0,25

Gate trigger current

VD=5V

V GD

Non-trigger gate voltage, min.

Peak gate voltage (forward)

Peak gate current

VD=VDRM

140

V FGM

FGM

V RGM

P GM

P G

Peak gate voltage (reverse)

Peak gate power dissipation

Average gate power dissipation

Pulse width 100 µs

150

MOUNTING

R th(j-h)

R th(c-h)

T j

Thermal impedance, DC

Thermal impedance

Operating junction temperature

Mounting force

Junction to heatsink, double side cooled

Case to heatsink, double side cooled

9,5

°C/kW

°C

-30 / 140

40,0 / 50,0

1150

Mass

ORDERING INFORMATION : AT708LT S 08

VRRM/100

standard specification

12 3 4

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