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AT22V10L-30KMB PDF预览

AT22V10L-30KMB

更新时间： 2024-01-15 18:57:31
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程逻辑器件
页数 文件大小 规格书
11页 274K
描述
Programmable Logic Device, PAL-Type, CMOS, CQCC28

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AT22V10L-30KMB 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DFP包装说明：WDFP, FL24,.4
针数：24Reach Compliance Code：unknown
ECCN代码：3A001.A.2.CHTS代码：8542.39.00.01
风险等级：5.26Is Samacsys：N
其他特性：10 FLIP FLOPS架构：PAL-TYPE
最大时钟频率：25 MHzJESD-30 代码：R-GDFP-F24
JESD-609代码：e0长度：15.45 mm
专用输入次数：11I/O 线路数量：10
输入次数：22输出次数：10
产品条款数：132端子数量：24
最高工作温度：125 °C最低工作温度：-55 °C
组织：11 DEDICATED INPUTS, 10 I/O输出函数：REGISTERED
封装主体材料：CERAMIC, GLASS-SEALED封装代码：WDFP
封装等效代码：FL24,.4封装形状：RECTANGULAR
封装形式：FLATPACK, WINDOW电源：5 V
可编程逻辑类型：UV PLD传播延迟：30 ns
认证状态：Not Qualified座面最大高度：2.41 mm
子类别：Programmable Logic Devices最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：FLAT端子节距：1.27 mm
端子位置：DUAL宽度：9.6 mm
Base Number Matches：1

AT22V10L-30KMB 数据手册

 浏览型号AT22V10L-30KMB的Datasheet PDF文件第3页浏览型号AT22V10L-30KMB的Datasheet PDF文件第4页浏览型号AT22V10L-30KMB的Datasheet PDF文件第5页浏览型号AT22V10L-30KMB的Datasheet PDF文件第7页浏览型号AT22V10L-30KMB的Datasheet PDF文件第8页浏览型号AT22V10L-30KMB的Datasheet PDF文件第9页 
Preload of Registered Outputs  
The registers in the AT22V10 and AT22V10L are provided  
with circuitry to allow loading of each register asynchronously  
with either a high or a low. This feature will simplify testing  
since any state can be forced into the registers to control test  
Level forced on  
registered output pin  
during preload cycle  
Register state  
after cycle  
sequencing. A V level on the I/O pin will force the register  
IH  
V
V
High  
Low  
IH  
high; a V will force it low, independent of the polarity bit (C0)  
IL  
setting. The preload state is entered by placing an 11.5-V to  
13-V signal on pin 8 on DIPs, and pin 10 on SMPs. When the  
clock pin is pulsed high, the data on the I/O pins is placed into  
the ten registers.  
IL  
tD  
tD  
tD  
tD  
tD  
t
= 100 ns  
DMIN  
VH  
PRELOAD  
CLOCK  
REGISTERED  
OUTPUTS  
OUTPUT  
PRELOADENA. FORCEI/O’S PRELOAD DATA  
OUTPUTSDIS. TO VIH ORVIL CLOCKEDIN  
VOLTAGE  
REMOVED  
PRELOAD  
DISABLED  
Power Up Reset  
3.8 V  
The registers in the AT22V10 and AT22V10L are designed to  
POWER  
reset during power up. At a point delayed slightly from V  
CC  
tPR  
crossing 3.8 V, all registers will be reset to the low state. The  
output state will depend on the polarity of the output buffer.  
REGISTERED  
OUTPUTS  
This feature is critical for state machine initialization. However,  
due to the asynchronous nature of reset and the uncertainty of  
tS  
how V actually rises in the system, the following conditions  
are required:  
CC  
tW  
CLOCK  
1) The V rise must be monotonic,  
CC  
2) After reset occurs, all input and feedback setup times must be  
met before driving the clock pin high, and  
Description  
Parameter  
Min Typ Max Units  
3) The clock must remain stable during t .  
PR  
Power-Up  
Reset Time  
t
600 1000  
ns  
PR  
Pin Capacitance (f = 1 MHz, T = 25°C) (1)  
Typ  
Max  
8
Units  
pF  
Conditions  
C
C
5
6
V
V
= 0 V  
IN  
IN  
8
pF  
= 0 V  
OUT  
OUT  
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.  
Erasure Characteristics  
The entire fuse array of an AT22V10 or AT22V10L is erased  
after exposure to ultraviolet light at a wavelength of 2537 Å.  
Complete erasure is assured after a minimum of 20 minutes ex-  
tensity ratings can be calculated from the minimum integrated  
erasure dose of 15 W• sec/cm . To prevent unintentional era-  
sure, an opaque label is recommended to cover the clear window  
on any UV erasable PLD which will be subjected to continuous  
fluorescent indoor lighting or sunlight.  
2
2
posure using 12,000 µW/cm intensity lamps spaced one inch  
away from the chip. Minimum erase time for lamps at other in-  
1-102  
AT22V10/L  
1...3456789...11

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