ASM3P1819N
PD#
VDD
PLL
Modulation
XIN
Frequency
Divider
Crystal
Oscillator
XOUT
Output
Divider
Phase
Detector
Loop
Filter
VCO
Feedback
Divider
REF
ModOUT
VSS
Figure 1. Block Diagram
Table 1. PIN DESCRIPTION
Pin#
Pin Name
XIN
Type
Description
1
2
3
4
5
6
I
Connect to externally generated Clock signal or Crystal.
Ground Connection. Connect to system ground.
No Connect.
VSS
P
−
O
O
I
NC
ModOUT
REF
Spread spectrum clock output.
Non−modulated Reference clock output of the input frequency.
PD#
Power down control pin. Pull LOW to enable Power−Down mode. This pin has an intern-
al pull−up resistor.
7
8
VDD
P
I
Connect to +3.3 V.
XOUT
Connect to crystal. No connect if externally generated clock signal is used.
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Rating
−0.5 to +4.6
−65 to +125
−40 to +85
260
Unit
V
VDD, V
Voltage on any pin with respect to Ground
Storage temperature
IN
T
STG
°C
°C
°C
°C
KV
T
A
Operating temperature
T
Max. Soldering Temperature (10 sec)
Junction Temperature
s
T
J
150
T
DV
Static Discharge Voltage (As per JEDEC STD22− A114−B)
2
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. OUTPUT FREQUENCY AND MODULATION RATE
Input Frequency Range (MHz)
Output Frequency Range (MHz)
Modulation Rate
Spread Deviation (%)
20 to 40
20 to 40
Input Frequency / 512
−1.25
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