AS7C34096-15BI

更新时间： 2024-01-21 18:48:48

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
9页	247K
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AS7C34096-15BI 数据手册

AS7C4096

AS7C34096

Functional description

The AS7C4096 and AS7C34096 are high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) devices

organized as 524,288 words × 8 bits. They are designed for memory applications where fast data access, low power, and simple

interfacing are desired.

Equal address access and cycle times (t , t , t ) of 10/12/15/20 ns with output enable access times (t ) of 5/6/7/8 ns are

AA RC WC

ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank

memory systems.

When CE is high the device enters standby mode. The AS7C4096/AS7C34096 is guaranteed not to exceed 110/72 mW power

consumption in CMOS standby mode.

A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1–I/O8 is

written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/

O pins only after outputs have been disabled with output enable (OE) or write enable (WE).

A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip

drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or

write enable is active, output drivers stay in high-impedance mode.

All chip inputs and outputs are TTL-compatible, and operation is from either a single 5V(AS7C4096) or 3.3V(AS7C34096)

supply. Both devices are available in the JEDEC standard 400-mil 36-pin SOJ and 44-pin TSOP 2 packages.

Absolute maximum ratings

Parameter

Device

Symbol

Min

–1

Max

+7.0

+5.0

Unit

AS7C4096

AS7C34096

Voltage on V relative to GND

–0.5

–

Voltage on any pin relative to GND

Power dissipation

+0.5

1.0

Storage temperature

–65

–55

–

+150

+125

°C

stg

bias

Temperature with V applied

DC current unto output (low)

OUT

NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-

tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect reliability.

Truth table

Data

Mode

Standby (I , I

High Z

)

SB SB1

Output disable (I

)

Read (I

)

OUT

Write (I

)

Key: X = Don’t care, L = Low, H = High

1/13/05; v.1.9

Alliance Semiconductor

P. 2 of 9

123 4 5 6 7...9

中文翻译

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与AS7C34096-15BI相关器件

型号	品牌	获取价格	描述	数据表
AS7C34096-15JC	ALSC	获取价格	5V/3.3V 512K X8 CMOS SRAM
AS7C34096-15JCN	ALSC	获取价格	5V/3.3V 512K X8 CMOS SRAM
AS7C34096-15JI	ALSC	获取价格	5V/3.3V 512K X8 CMOS SRAM
AS7C34096-15JIN	ALSC	获取价格	5V/3.3V 512K X8 CMOS SRAM
AS7C34096-15TC	ALSC	获取价格	5V/3.3V 512K X8 CMOS SRAM
AS7C34096-15TCN	ALSC	获取价格	5V/3.3V 512K X8 CMOS SRAM
AS7C34096-15TI	ALSC	获取价格	5V/3.3V 512K X8 CMOS SRAM
AS7C34096-15TIN	ALSC	获取价格	5V/3.3V 512K X8 CMOS SRAM
AS7C34096-20	ALSC	获取价格	5V/3.3V 512K X8 CMOS SRAM
AS7C34096-20JC	ALSC	获取价格	5V/3.3V 512K X8 CMOS SRAM

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