Datasheet > AS4LC1M16EC-6

AS4LC1M16EC-6

更新时间： 2024-02-25 16:28:06

品牌	Logo	应用领域
MICROSS		动态存储器
页数	文件大小	规格书
22页	195K
描述
DRAM

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AS4LC1M16EC-6 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.75
Base Number Matches：	1

AS4LC1M16EC-6 数据手册

AS4LC1M16 883C

1 MEG x 16 DRAM

AUSTIN SEMICONDUCTOR, INC.

DRAM

1 MEG x 16^PD^RER^LIMIA^NARM^Y

3.3V, EDO PAGE MODE,

OPTIONAL EXTENDED REFRESH

AVAILABLE AS MILITARY

SPECIFICATIONS

PIN ASSIGNMENT (Top View)

•

MIL-STD 883

44/50-Pin SOJ/LCC/Gull Wing

•

SMD Planned

450mil

FEATURES

•

JEDEC- and industry-standard x16 timing, functions,

pinouts and packages

High-performance CMOS silicon-gate process

Single +3.3V ±0.3V power supply

All device pins are TTL-compatible

Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR),

HIDDEN

Vcc

DQ1

DQ2

DQ3

DQ4

Vcc

DQ5

DQ6

DQ7

DQ8

Vss

DQ16

DQ15

DQ14

DQ13

Vss

DQ12

DQ11

DQ10

DQ9

•

BYTE WRITE access cycles

1,024-cycle refresh (10 row-, 10 column-addresses)

Low power, 0.3mW standby; 180mW active, typical

Extended Data-Out (EDO) PAGE access cycle

5V-tolerant I/ Os (5.5V maximum V^IHlevel)

RAS

Vcc

CASL

CASH

OPTIONS

•

MARKING

Timing

60ns access (Contact Factory)

70ns access

80ns access

-6

-7

-8

Vss

•

Refresh Rate

Standard 16ms period

None

Packages

Ceramic SOJ

Ceramic Gull Wing

Ceramic LCC

ECJ No. 506

ECG No. 604

EC No. 213

an internal CAS.

The AS4LC1M16 CAS function and timing are deter-

mined by the first CAS (CASL or CASH) to transition LOW

and the last CAS to transition back HIGH. Use of only one

ofthetworesultsin a BYTEWRITEcycle.CASLtransitioning

LOW selects an access cycle for the lower byte (DQ1-DQ8)

and CASH transitioning LOW selects an access cycle for the

upper byte (DQ9-DQ16).

KEY TIMING PARAMETERS

SPEED

-6

^tRC

^tRAC

60ns

70ns

80ns

^tPC

^tAA

30ns

35ns

40ns

^tCAC

15ns

20ns

^tCAS

12ns

20ns

105ns

125ns

150ns

25ns

30ns

40ns

-7

-8

GENERAL DESCRIPTION

Each bit is uniquely addressed through the 20address bits

during READ or WRITE cycles. These are entered 10 bits

(A0-A9) at a time. RAS is used to latch the first 10 bits and

CAS the latter 10 bits. The CAS function also determines

whether the cycle will be a refresh cycle (RAS ONLY) or an

active cycle (READ, WRITE or READ WRITE) once RAS

goes LOW.

The AS4LC1M16 is a randomly accessed solid-state

memory containing 16,777,216 bits organized in a x16 con-

figuration. The AS4LC1M16 has both BYTE WRITE and

WORD WRITE access cycles via two CAS pins (CASL and

CASH). These function in a similar manner to a single CAS

of other DRAMs in that either CASL or CASH will generate

AS4LC1M16

REV. 3/97

DS000020

Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.

2-93

12 3 4 5 6 7...22

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AS4LC1M16EC6/883	MICROSS	EDO DRAM, 1MX16, 60ns, CMOS, CDSO44	获取价格
AS4LC1M16EC-6/883C	MICROSS	EDO DRAM, 1MX16, 60ns, CMOS, CDSO44, 0.450 INCH, CERAMIC, LCC-50/44	获取价格
AS4LC1M16EC-7	MICROSS	DRAM	获取价格
AS4LC1M16EC7/883	MICROSS	EDO DRAM, 1MX16, 70ns, CMOS, CDSO44	获取价格
AS4LC1M16EC-7/883C	MICROSS	EDO DRAM, 1MX16, 70ns, CMOS, CDSO44, 0.450 INCH, CERAMIC, LCC-50/44	获取价格
AS4LC1M16EC-8	MICROSS	DRAM,	获取价格

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