Datasheet > AP2151A

AP2151A

更新时间： 2023-12-06 20:11:34

品牌	Logo	应用领域
美台 - DIODES		/
页数	文件大小	规格书
18页	887K
描述
0.5A Single Channel Current-Limited Power Switch

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AP2151A 数据手册

AP2151A

Electrical Characteristics (@T_A= +25°C, V_IN= +5.0V, unless otherwise specified.)

Symbol

V_UVLO

I_SHDN

I_Q

Parameter

Conditions

Min

1.6

—

Typ

1.9

0.5

—

Max

2.5

Unit

Input UVLO

R_LOAD= 1kΩ

Input Shutdown Current

Input Quiescent Current

Input Leakage Current

Reverse Leakage Current

µA

Disabled, I_OUT= 0

Enabled, I_OUT= 0

—

Disabled, OUT grounded

—

I_LEAK

I_REV

—

Disabled, V_IN= 0V, V_OUT= 5V, I_REVat V_IN

SOT25, SO-8, MSOP-8EP

U-DFN2018-6

—

115

110

140

T_A= +25°C

V_IN= 5V,

—

I_OUT= 0.5A

—

-40°C ≤ T_A≤ +85°C

T_A= +25°C

Switch On-Resistance

mΩ

R_DS(ON)

—

0.6

—

120

—

140

170

—

V_IN= 3.3V,

I_OUT= 0.5A

-40°C ≤ T_A≤ +85°C

Short-Circuit Current Limit

Over-Load Current Limit

0.6

0.8

1.0

—

I_SHORT

I_LIMIT

I_TRIG

I_SINK

t_D(ON)

t_R

Enabled into short circuit, C_L= 22µF

V_IN= 5V, V_OUT= 4.8V, C_L= 22µF, -40C ≤ T_A≤ +85°C

Output Current Slew Rate (<100A/s), C_L= 22µF

V_EN= 5V

1.0

—

Current Limiting Trigger Threshold

EN Input Leakage

µA

Ω

Output Turn-On Delay Time

Output Turn-On Rise Time

Output Turn-Off delay Time

Output Turn-Off Fall Time

FLG Output FET On-Resistance

FLG Blanking Time

0.05

0.6

0.01

0.05

—

C_L= 1µF, R_LOAD= 10Ω

1.5

—

C_L= 1µF, R_LOAD= 10Ω

t_D(OFF)

t_F

C_L= 1µF, R_LOAD= 10Ω

0.1

C_L= 1µF, R_LOAD= 10Ω

R_FLG

t_BLANK

T_SHDN

T_HYS

I_FLG=10mA

C_IN= 10µF, C_L= 22µF

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

—

+140

+25

110

—

°C

Enabled, R_LOAD= 1kΩ

—

°C

SO-8 (Note 6)

°C/W

MSOP-8EP (Note 7)

SOT25 (Note 8)

U-DFN2018-6 (Note 9)

Thermal Resistance Junction-to-

Ambient

θ_JA

157

Notes:

6. Test condition for SO-8: Device mounted on FR-4, 2oz copper, with minimum recommended pad layout.

7. Test condition for SO-8, MSOP-8EP: Device mounted on 2” x 2” FR-4 substrate PC board, 2oz copper, with minimum recommended pad on top layer

and thermal vias to bottom layer ground plane.

8. Test condition for SOT25: Device mounted on FR-4, 2oz copper, with minimum recommended pad layout.

9. Test condition for U-DFN2018-6: Device mounted on FR-4 2-layer board, 2oz copper, with minimum recommended pad on top layer and 3 vias to bottom

layer 1.0” x 1.4” ground plane.

4 of 18

www.diodes.com

January 2018

AP2151A

Document number: DS37615 Rev. 2 - 2

1 2 345 6 7...18

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