Datasheet > AMS73CAG02168RALJH8I

AMS73CAG02168RALJH8I

更新时间： 2022-10-09 17:13:05

品牌	Logo	应用领域
奥地利微 - AMS		动态存储器双倍数据速率
页数	文件大小	规格书
31页	683K
描述
HIGH PERFORMANCE 1Gbit DDR3 SDRAM

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数据手册

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AMS73CAG02168RALJH8I 数据手册

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AMS73CAG01808RA

HIGH PERFORMANCE 1Gbit DDR3 SDRAM

8 BANKS X 16Mbit X 8

- H7

- I9

DDR3-1333

2.5 ns

DDR3-1066

2.5 ns

1.875 ns

Clock Cycle Time ( t_{CK6, CWL=5}

Clock Cycle Time ( t_{CK7, CWL=6}

Clock Cycle Time ( t_{CK8, CWL=6}

Clock Cycle Time ( t_{CK9, CWL=7}

)

1.875 ns

1.5 ns

Clock Cycle Time ( t_{CK10, CWL=7}

System Frequency (f_{CK max}

)

1.5 ns

)

533 MHz

667 MHz

Specifications

Features

Double-data-rate architecture; two data transfers per

clock cycle

Density : 1G bits

Organization : 16M words x 8 bits x 8 banks

Package :

The high-speed data transfer is realized by the 8 bits

prefetch pipelined architecture

- 78-ball FBGA

- Lead-free (RoHS compliant) and Halogen-free

Power supply : VDD, VDDQ = 1.5V ± 0.075V

Data rate : 1333Mbps/1066Mbps (max.)

1KB page size

Bi-directional differential data strobe (DQS and DQS)

is transmitted/received with data for capturing data at

the receiver

DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

- Row address: A0 to A13

- Column address: A0 to A9

Eight internal banks for concurrent operation

Interface : SSTL_15

Burst lengths (BL) : 8 and 4 with Burst Chop (BC)

Burst type (BT) :

Differential clock inputs (CK and CK)

DLL aligns DQ and DQS transitions with CK transitions

Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

Data mask (DM) for write data

- Sequential (8, 4 with BC)

- Interleave (8, 4 with BC)

Posted CAS by programmable additive latency for bet-

ter command and data bus efficiency

CAS Latency (CL) : 5, 6, 7, 8, 9, 10, 11

CAS Write Latency (CWL) : 5, 6, 7, 8

Precharge : auto precharge option for each burst ac-

cess

Driver strength : RZQ/7, RZQ/6 (RZQ = 240 Ω)

Refresh : auto-refresh, self-refresh

Refresh cycles :

On-Die Termination (ODT) for better signal quality

- Synchronous ODT

- Dynamic ODT

- Asynchronous ODT

Multi Purpose Register (MPR) for pre-defined pattern

read out

ZQ calibration for DQ drive and ODT

- Average refresh period

7.8 μs at 0°C ≤ Tc ≤ +85°C

3.9 μs at +85°C < Tc ≤ +95°C

Operating case temperature range

- Tc = 0°C to +95°C

Programmable Partial Array Self-Refresh (PASR)

RESET pin for Power-up sequence and reset function

SRT range : Normal/extended

Programmable Output driver impedance control

Device Usage Chart

Operating

Temperature

Range

Package Outline

Speed

Power

Temperature

78-ball FBGA

- H7

- I9

Std.

•

Mark

Blank

0°C ≤ Tc ≤ 95°C

•

-40°C ≤ Tc ≤ 95°C

•

AMS73CAG01808RA Rev.1.0 December 2010

12 3 4 5 6 7...31

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与AMS73CAG02168RALJH8I相关器件

型号	品牌	描述	获取价格	数据表
AMS73CAG02168RALJI8	AMS	HIGH PERFORMANCE 1Gbit DDR3 SDRAM	获取价格
AMS73CAG02168RALJI8E	AMS	HIGH PERFORMANCE 1Gbit DDR3 SDRAM	获取价格
AMS73CAG02168RALJI8H	AMS	HIGH PERFORMANCE 1Gbit DDR3 SDRAM	获取价格
AMS73CAG02168RALJI8I	AMS	HIGH PERFORMANCE 1Gbit DDR3 SDRAM	获取价格
AMS73CAG02168RALJI9	AMS	HIGH PERFORMANCE 1Gbit DDR3 SDRAM	获取价格
AMS73CAG02168RALJI9E	AMS	HIGH PERFORMANCE 1Gbit DDR3 SDRAM	获取价格

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