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AMIS-732512 PDF预览

AMIS-732512

更新时间: 2024-02-15 23:45:23
品牌 Logo 应用领域
AMI 光电二极管光电二极管
页数 文件大小 规格书
9页 285K
描述
50レm-pitch Wide Aperture Spectroscopic Photodiode Arrays

AMIS-732512 技术参数

生命周期:TransferredReach Compliance Code:compliant
HTS代码:8541.40.60.50风险等级:5.01
Is Samacsys:N配置:SINGLE
最大暗电源:600 nA红外线范围:NO
功能数量:1峰值波长:600 nm
形状:RECTANGULAR尺寸:25.6 mm
Base Number Matches:1

AMIS-732512 数据手册

 浏览型号AMIS-732512的Datasheet PDF文件第3页浏览型号AMIS-732512的Datasheet PDF文件第4页浏览型号AMIS-732512的Datasheet PDF文件第5页浏览型号AMIS-732512的Datasheet PDF文件第7页浏览型号AMIS-732512的Datasheet PDF文件第8页浏览型号AMIS-732512的Datasheet PDF文件第9页 
AMIS-732128, AMIS-732256, AMIS-732512  
Data Sheet  
50µm-pitch Wide Aperture Spectroscopic Photodiode Arrays  
Table 2: Symbol Definitions and Timing Specifications for Timing Diagram  
Item  
Symbol  
Min.  
666 (AMIS-732128)  
666 (AMIS-732256)  
1000 (AMIS-732512)  
566 (128WSN)  
566 (256WSN)  
900 (512WSN)  
100  
Typ.  
Max.  
Units  
Clock cycle time  
to  
10000  
ns  
Clock high pulse width  
twh  
twl  
ns  
Clock low pulse width  
Clock duty cycle  
ns  
%
1
50  
99  
Data setup time  
Data hold time  
EOS low-to-high delay  
EOS high-to-low delay  
Signal delay time  
tds  
tdh  
telh  
tehl  
tsd  
100  
100  
ns  
ns  
ns  
ns  
ns  
400  
400  
50  
0
566 (AMIS-732128)  
566 (AMIS-732256)  
900 (AMIS-732512)  
Signal settling time  
tsh  
ns  
ns  
Signal settle to clock edge  
tsch  
7.0 Recommended Operating Conditions  
The following table lists the recommended operating conditions.  
Table 3: Recommended Operating Conditions at 25oC  
Parameters  
Power supply  
Symbol  
VDD  
Vih  
Vil  
Vbias  
Min.  
4.5  
VDD – 0.8  
0.0  
VDD – 0.5  
Typ.  
5.0  
VDD  
Max.  
5.5  
VDD  
0.8  
VDD  
Units  
V
V
V
V
Input clock pulses high level 1  
Input clock pulse low level 1  
Video charge output external bias  
0.0  
VDD – 0.5  
1.5 (AMIS-732128)  
1.5 (AMIS-732256)  
1.0 (AMIS-732512)  
Clock frequency  
Fclk  
Tint  
0.1  
MHz  
ms  
0.09 (AMIS-732128)  
0.18 (AMIS-732256)  
0.52 (AMIS-732512)  
Integration time 2  
9000  
Notes:  
1.  
2.  
Applies to all control-clock inputs.  
The Integration time is specified at room temperature such that the maximum dark current charge build up in each pixel is less than 10 percent of the minimum  
saturation charge. Accordingly, it may be as long as nine seconds at room temperature. Longer integration times may be achieved by cooling the device. An  
appropriate clock frequency must be chosen so that the shift register completes its operation within the desired integration time.  
AMI Semiconductor – Dec. 05, M-20491-001  
6
www.amis.com  

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