Datasheet > AM45DL6408G85IS

AM45DL6408G85IS

更新时间： 2024-01-21 11:23:57

品牌	Logo	应用领域
飞索 - SPANSION		静态存储器内存集成电路
页数	文件大小	规格书
65页	1101K
描述
Memory Circuit, 4MX16, CMOS, PBGA73, 8 X 11.60 MM, FBGA-73

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技术参数
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AM45DL6408G85IS 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	LFBGA,
针数：	73	Reach Compliance Code：	compliant
HTS代码：	8542.32.00.71	风险等级：	5.08
其他特性：	PSEUDO SRAM IS ORGANISED AS 1M X 8 OR 512K X 16; FLASH CAN ALSO BE ORGANISED AS 8M X 8	JESD-30 代码：	R-PBGA-B73
JESD-609代码：	e0	长度：	11.6 mm
内存密度：	67108864 bit	内存集成电路类型：	MEMORY CIRCUIT
内存宽度：	16	湿度敏感等级：	3
功能数量：	1	端子数量：	73
字数：	4194304 words	字数代码：	4000000
工作模式：	ASYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	4MX16
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFBGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	240	认证状态：	Not Qualified
座面最大高度：	1.4 mm	最大供电电压 (Vsup)：	3.3 V
最小供电电压 (Vsup)：	2.7 V	标称供电电压 (Vsup)：	3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	TIN LEAD
端子形式：	BALL	端子节距：	0.8 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	30
宽度：	8 mm	Base Number Matches：	1

AM45DL6408G85IS 数据手册

PRELIMINARY

Am45DL6408G

Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash

Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Pseudo Static RAM

DISTINCTIVE CHARACTERISTICS

■ Minimum 1 million erase cycles guaranteed per sector

MCP Features

■ 20 year data retention at 125°C

Reliable operation for the life of the system

■ Power supply voltage of 2.7 to 3.3 volt

—

■ High performance

—

Access time as fast as 70 ns

SOFTWARE FEATURES

■ Package

■ Data Management Software (DMS)

—

73-Ball FBGA

—

AMD-supplied software manages data programming,

enabling EEPROM emulation

■ Operating Temperature

—

Eases historical sector erase flash limitations

—

–40°C to +85°C

■ Supports Common Flash Memory Interface (CFI)

Flash Memory Features

■ Program/Erase Suspend/Erase Resume

—

Suspends program/erase operations to allow

programming/erasing in same bank

ARCHITECTURAL ADVANTAGES

■ Simultaneous Read/Write operations

■ Data# Polling and Toggle Bits

—

Data can be continuously read from one bank while

executing erase/program functions in another bank.

Zero latency between read and write operations

—

Provides a software method of detecting the status of

program or erase cycles

—

■ Unlock Bypass Program command

■ Flexible Bank architecture

—

Reduces overall programming time when issuing multiple

program command sequences

—

Read may occur in any of the three banks not being written

or erased.

—

Four banks may be grouped by customer to achieve desired

bank divisions.

HARDWARE FEATURES

■ Any combination of sectors can be erased

■ Manufactured on 0.17 µm process technology

■ Ready/Busy# output (RY/BY#)

■ SecSi™ (Secured Silicon) Sector: Extra 256 Byte sector

—

Hardware method for detecting program or erase cycle

completion

—

Factory locked and identifiable: 16 bytes available for

secure, random factory Electronic Serial Number; verifiable

as factory locked through autoselect function. ExpressFlash

option allows entire sector to be available for

factory-secured data

■ Hardware reset pin (RESET#)

—

Hardware method of resetting the internal state machine to

the read mode

—

Customer lockable: Sector is one-time programmable. Once

sector is locked, data cannot be changed.

■ WP#/ACC input pin

—

Write protect (WP#) function protects sectors 0, 1, 140, and

■ Zero Power Operation

Sophisticated power management circuits reduce power

consumed during inactive periods to nearly zero.

■ Boot sectors

141, regardless of sector protect status

—

Acceleration (ACC) function accelerates program timing

■ Sector protection

—

Hardware method of locking a sector, either in-system or

—

Top and bottom boot sectors in the same device

using programming equipment, to prevent any program or

erase operation within that sector

■ Compatible with JEDEC standards

—

Temporary Sector Unprotect allows changing data in

protected sectors in-system

—

Pinout and software compatible with single-power-supply

flash standard

Pseudo SRAM Features

PERFORMANCE CHARACTERISTICS

■ Power dissipation

■ High performance

—

Operating: 30 mA maximum

Standby: 100 µA maximum

—

Access time as fast as 70 ns

Program time: 4 µs/word typical utilizing Accelerate function

■ CE1s# and CE2s Chip Select

■ Ultra low power consumption (typical values)

—

2 mA active read current at 1 MHz

10 mA active read current at 5 MHz

200 nA in standby or automatic sleep mode

■ Power down features using CE1s# and CE2s

■ Data retention supply voltage: 2.7 to 3.3 volt

■ Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)

Publication# 26018 Rev: B Amendment/+1

Issue Date: May 13, 2003

Refer to AMD’s Website (www.amd.com) for the latest information.

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与AM45DL6408G85IS相关器件

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