ALED6001
Pin function
Table 2. Pin description
No.
Pin
1
PWMI
Device enable and PWM dimming control input.
Switching frequency setting. A resistor between this pin and SGND sets the
desired switching frequency. This pin is also used as synchronization input. If tied
high (e.g.: connected to LDO3 pin) a 600 kHz switching frequency is set.
2
FSW
Fault indicator, open-drain output. This pin is tied low by the device in case of
faulty condition. See Section 7.4 on page 20 for details.
3
4
5
XFAULT
LDO3
3.3 V linear regulator output and device supply. Connect a 1 μF (typ.) bypass
MLCC between this pin and SGND as close as possible to the chip.
Signal ground. Return for analog circuitry. All setting components must refer to this
grounding pin.
SGND
Boost controller loop compensation. A simple RC series must be connected
6
7
COMP between this pin and SGND for proper loop compensation. See Section 7.2.3 on
page 14 for details.
Analog dimming control input. The current at the output is linearly controlled by the
voltage applied to this pin (0.3 V to 1.2 V). When the device is set to operate in
standalone mode, a partition of the LDO3 voltage must be applied to this pin
ADIM
through a resistor divider.
Output overvoltage protection feedback input. Connect to the central tap of
a resistor divider at the output.
8
9
OVFB
Boost controller power switch current sensing input. Connect to the source of the
external Power MOSFET for proper switch overcurrent protection.
CSNS
PWM dimming control output. This pin provides a PWM output signal (in phase
PWMO with the one applied to the PWMI pin) for direct control of a dimming N-channel
MOSFET.
10
11
Power ground. Return for the VDR linear regulator and the power switch gate
drivers. Also used as reference for the Power MOSFET current sensing circuitry.
Connect to ground as close as possible to the quiet terminal of the power switch
PGND
sensing resistor.
Power switch gate driver output. Connect to the gate of the Power MOSFET
through a small value resistor.
12
13
GATE
5 V linear regulator output and gate driver supply. Connect a 1 μF (typ.) bypass
MLCC between this pin and PGND as close as possible to the chip.
VDR
Supply voltage input. Connect this pin to the supply power rail. A 1 μF (typ.)
bypass MLCC must be connected between this pin and PGND as close as
possible to the chip.
14
VIN
Output current differential sensing input, negative terminal. Connect to the hot
terminal (load side) of the high-side sensing resistor.
15
16
-
VFBN
VFBP
TPAD
Output current differential sensing input, positive terminal. Connect to the quiet
terminal (output capacitor side) of the high-side sensing resistor.
Thermal pad. Connect to a suitable ground plane area in order to ensure proper
heat dissipation. Electrically connected to PGND and SGND.
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