Datasheet > AK5522VN

AK5522VN

更新时间： 2022-02-26 13:29:59

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AKM		/
页数	文件大小	规格书
84页	1886K
描述
Differential Input Stereo 32-bit ADC with Excellent PSRR

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AK5522VN 数据手册

[AK5522]

AK5522

Differential Input Stereo 32-bit  ADC with Excellent PSRR

1. General Description

The AK5522 is a 32-bit, from 8kHz to 192kHz sampling A/D converter for line and microphone inputs of

digital audio systems. It achieves 108dB dynamic range and 98dB S/(N+D) while keeping low power

consumption performance. Four types of digital filters are integrated and selectable according to the

sound quality preference.

The AK5522 has great power supply rejection ratio, (PSRR), and common mode rejection ratio, (CMRR),

enabling to maintain sufficient characteristics when connecting USB bus power or DCDC converter

output as a power supply. It is suitable for applications with noisy power supply such as USB audio

interface, wireless speakers and car audio equipment.

In addition, the AK5522 integrates a regulator with high PSRR for DAC power supply. Using the AK5522

with a DAC such as the AK4432 or the AK4452, it is enable to bring maximum DAC performance even in

a poor power supply condition. Moreover, the AK5522 integrates low-jitter PLL circuit that generates a

master clock for DAC from LRCK or BICK. It provides a low-EMI solution by avoiding unnecessary

drawing of the master clock that has high frequency, on the board.

The AK5522 helps reducing components and a mounting space with these features for environmental

noise.

2. Features

 Sampling Rate:

 Input:

8kHz - 192kHz

Full Differntial, Pseudo Differential, Single-Ended

 S/(N+D):

98dB typ.

 DR, S/N:

108dB typ.

 PSRR:

80dB typ.

 CMRR:

80dB typ.

 Internal Filter:

 Short Group Delay:

 Output Format:

 Operation Mode:

Four types of LPF, Digital HPF

4.4/fs (Short Delay Slow roll-off)

32-bit MSB justified, I²S or TDM (Cascade Connection available)

Master or Slave Modes

 Programmable Gain Amp: 3dB - +12dB/1dB (Fixed at 0dB in Parallel Control mode)

 Integrated PLL:

Generates the master clock from BICK or LRCK

 Master Clock Output:

Output master clock generated by the PLL

 Voltage Regulator for External DAC Power: Generates 3.3V from 5V applied to AVDD pin.

 Power Supply:

 Control Mode:

Analog 4.5 - 5.5V or 3.0 - 3.6V, Digital 3.0 - 3.6V or 1.7 - 1.98V

Parallel Control mode (Pin setting)

Serial Control mode (I²C Bus setting)

76 mW (@AVDD=5.0V, DVDD=3.3V, fs=48kHz)

40 - 105C

 Power Consumption:

 Operation Temperature:

 Package:

24-pin QFN 4mmx4mm, 0.5mm pitch

017002311-E-00

2017/03

- 1 -

12 3 4 5 6 7...84

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