AK2048D

更新时间： 2024-02-17 13:18:42

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AK2048D 技术参数

ASAHI KASEI

[AK2048]

FUNCTIONAL DESCRIPTION

PLL calibration function

The calibration of PLL is caused in case of the following 3cases.

(1) Power on

(2) RST rising

(3) LOCK rising

(1) Power on

After the power is on, the calibration is complete and LOCK goes to “Low” in less than 63ms from

whichever the later happens, the input of signal (RXA-RXB) or the rising edge of RST.

(2) RST rising

The calibration is complete and LOCK goes to “Low” in less than 38ms from whichever the later

happens, the input of signal (RXA-RXB) or the rising edge of RST.

(3) LOCK rising

When the device falls into unlock by some reasons and LOCK goes to “high”, calibration restarts.

The calibration is complete and LOCK goes to “Low” in less than 38ms from the rising edge of LOCK.

PLL pull in time after loss of signal

When LOS goes to “high” by loss of signal after the calibration, the pull in of the PLL restarts by

signal input. If the device can pull in without calibration, pull-in completes less than 200us.

In other case, LOCK goes to “high” and calibration restarts less than 2ms.

LOS signal

LOS goes to ”high”, when the amplitude of RXB is less than 135mVpp(typ) during 16 bits (about 8us).

LOS signal goes to “Low”, when amplitude of RXB is more than 135mVpp(typ).

When the signal is lost during the calibration, LOS signal goes to “high” and the calibration circuit is

reset. The calibration restarts after LOS signal goes to “Low”.

MS0073-E-00

2001/01

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