Datasheet > AI4100

AI4100

更新时间： 2024-01-14 02:55:56

品牌	Logo	应用领域
A1PROS		/
页数	文件大小	规格书
18页	382K
描述
CCD CDS/PGA/10b-20M-ADC

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中文翻译

获取价格

数据手册

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AI4100 数据手册

Ai4100

FUNCTIONAL DESCRIPTION

CDS (Correlated Double Sampling) Circuit

Clamp target (Mode 2 register D5 and D4), input

signal(REFIN and CCDIN) to be clamped are selected.

Connect the CCDIN pin to the CCD sensor through a

capacitor. Connect also the REFIN pin to V_SSthrough a

capacitor. The CDS circuit holds the pre-charge voltage of

the CCD at SHP pulse and do sampling of the CCD pixel

data at SHD pulse, Correlated noise is removed by

subtracting the pre-charge voltage from the pixel data level.

CDS could choose a gain setting from 0, 6.02, 12 or -1.94dB

(Mode 3, register D4 and D5 bits). A CDS gain is controlled

by PGA gain. It is recommended to increase the CDS gain

then increase the PGA gain to reduce the noise level.

CDS (Correlated Double Sampling) Circuit

The purpose of a black level cancel circuit is to control

the DC level of the PGA input. The ADC output code

at an optical black period may correspond to the black

level code set up by the register. A black level code of

(1 to)16 to 127 LSB is available (the default is 64 LSB)

While the OBP pin is active a black level cancel loop is

established. In the loop, a comparison is made

between the ADC output code and the black level

code, the result controls the voltage of the OBCAP

capacitor. Hence, the OBCAP voltage settles gradually

and the signal level of the optical black period

corresponds to the established value.

Clamp Circuits

DC clamp

The DC level of the CCDIN/REFIN input is fixed by an

internal DC clamp circuit. The DC level of the C-coupled

CCD signal at the CDS input is set to CLPCAP by the

internal DC clamp circuit. The clamp switches are usually

turned on at the black level calibration period. The

CLPCAP pin connects to VSS through a 0.1μF capacitor.

The following conditions will reset the OBCAP capaci-

tor:

ADIN signal clamp

Set the black level reset register to “1”

(Mode 1 register D1=1).

Clamp operation can also be used for the ADIN path. The

clamp voltage is different from the CCDIN/REFIN signal

and it could be turned off by register setting. At “ADIN

signal to ADC” mode, the ADCLP signal controls the “clamp

circuit”. Black level calibration circuit is also controlled by

ADCLP at “ADIN signal to PGA” mode

Set the RESETN pin to low

Power down by STBY pin or register control

The DC clamping (CCDCLP) is allowed while the DBP pin

is low. The black level cancellation is available at “ADIN

signal to PGA” mode. The black level cancellation is

available at the ADCLP period in this mode. The clamping

function and black level canceling function are done

simultaneously.

Clamp control

Clamp current (Mode 2 register D7). Charge current

can select normal or fast clamp.

CCD

Blanking

Effective Pixel

ADCLK

BLK

OBP

CCDCLP

OUTCK

Data Output

DO₀~DO₉

Black Code

1...3 4 567 8 9...18

中文翻译

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