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AFCT-5815AZ PDF预览

AFCT-5815AZ

更新时间: 2024-01-23 03:19:42
品牌 Logo 应用领域
安华高科 - AVAGO 光纤异步传输模式放大器ATM通信
页数 文件大小 规格书
10页 134K
描述
155 Mb/s Single Mode Fiber Optic Transceiver for ATM, SONET OC-3/SDH STM-1

AFCT-5815AZ 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:ROHS COMPLIANT PACKAGEReach Compliance Code:unknown
ECCN代码:5A991.B.5.AHTS代码:8517.62.00.50
风险等级:5.82主体宽度:25.4 mm
主体高度:9.8 mm主体长度或直径:39.6 mm
内置特性:AMPLIFIER通信标准:ATM, OC-3, SDH, SONET, STM-1
连接类型:SC CONNECTOR数据速率(接收):155 Mbps
数据速率(发送):155 Mbps发射极/检测器类型:PIN PHOTODIODE
光纤设备类型:TRANSCEIVER光纤类型:SMF
安装特点:PANEL MOUNT最高工作温度:85 °C
最低工作温度:-40 °C最大工作波长:1360 nm
最小工作波长:1261 nm标称工作波长:1311 nm
标称光功率输出:0.5623 mW灵敏度:-34 dBm
子类别:Fiber Optic Transceivers最大供电电压:5.25 V
最小供电电压:3.1 V标称供电电压:4.2 V
表面贴装:NO

AFCT-5815AZ 数据手册

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Recommended Circuit Schematic  
In order to ensure proper functionality of the AFCT-5815xZ  
a recommended circuit is provided in Figure 3. When de-  
signing the circuit interface, there are a few fundamental  
guidelines to follow. For example, in the Recommended  
Circuit Schematic figure the differential data lines should  
be treated as 50 ohm Microstrip or stripline transmission  
lines. This will help to minimize the parasitic inductance  
and capacitance effects. Proper termination of the dif-  
ferential data signals will prevent reflections and ringing  
which would compromise the signal fidelity and gener-  
ate unwanted electrical noise. Locate termination at the  
received signal end of the transmission line. The length  
of these lines should be kept short and of equal length.  
For the high speed signal lines, differential signals should  
be used, not single-ended signals, and these differential  
signals need to be loaded symmetrically to prevent un-  
balanced currents from flowing which will cause distor-  
tion in the signal.  
using the recommended, separate filter circuits shown in  
Figure 3 for the transmitter and receiver sections. These  
filter circuits suppress V noise over a broad frequency  
CC  
range, this prevents receiver sensitivity degradation due  
to V noise. It is recommended that surface-mount  
CC  
components be used. Use tantalum capacitors for the  
10 μF capacitors and monolithic, ceramic bypass capaci-  
tors for the 0.1 μF capacitors. Also, it is recommended  
that a surface- mount coil inductor of 3.3 μH be used.  
Ferrite beads can be used to replace the coil inductors  
when using quieter V supplies, but a coil inductor  
CC  
is recommended over a ferrite bead. All power supply  
components need to be placed physically next to the  
V
pins of the receiver and transmitter. Use a good, uni-  
CC  
form ground plane with a minimum number of holes to  
provide a low-inductance ground current return for the  
power supply currents.  
In addition to these recommendations, Avago Tech-  
nologies Application Engineering staff is available for  
consulting on best layout practices with various vendors  
mux/demux, clock generator and clock recovery circuits.  
Avago Technologies has participated in several reference  
design studies and is prepared to share the findings of  
these studies with interested customers. Contact your  
local Avago Technologies sales representative to arrange  
for this service.  
Maintain a solid, low inductance ground plane for re-  
turning signal currents to the power supply. Multilayer  
plane printed circuit board is best for distribution of V  
,
CC  
returning ground currents, forming transmission lines  
and shielding, Also, it is important to suppress noise  
from influencing the fiber-optic transceiver performance,  
especially the receiver circuit. Proper power supply  
filtering of V for this transceiver is accomplished by  
CC  
NO INTERNAL  
CONNECTION  
NO INTERNAL  
CONNECTION  
TOP VIEW  
Rx  
Rx  
VEER  
1
Tx  
Tx  
VEET  
9
VCCR VCCT  
RD  
2
SD  
4
TD  
8
RD  
3
TD  
7
5
6
NOTES:  
THE SPLIT-LOAD TERMINATIONS FOR PECL SIGNALS  
NEED TO BE LOCATED AT THE INPUT OF DEVICES  
RECEIVING THOSE PECL SIGNALS.  
RECOMMEND 4-LAYER PRINTED CIRCUIT BOARD WITH  
50MICROSTRIP SIGNAL PATHS BE USED.  
R1 = R4 = R6 = R8 = R10 = 130 FOR +5.0V OPERA-  
TION, 82 FOR +3.3V OPERATION.  
R2 = R3 = R5 = R7 = R9 = 82 FOR +5.0V OPERATION,  
130 FOR +3.3V OPERATION.  
C1 = C2 = 10 μF  
C3 = C4 = C7 = C8 = 100 nF  
C5 = C6 = 0.1 μF  
L1 = L2 = 3.3 μH COIL OR FERRITE INDUCTOR.  
C1 C7  
C2 C8  
VCC  
L1 L2  
R2  
R1  
R3  
VCC  
C3  
C4  
TERMINATE  
AT PHY  
R5  
R7  
C6  
C5  
Vcc FILTER  
AT Vcc PINS  
TRANSCEIVER  
R4  
DEVICE  
INPUTS  
TERMINATION  
AT  
R6  
R8  
TRANSCEIVER  
INPUTS  
R10 R9  
VCC  
TD  
TD  
RD  
RD  
SD  
Figure 3. Recommended Circuit Schematic  
3

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