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ADUM6403ARWZ

更新时间： 2024-01-07 13:47:03
品牌 Logo 应用领域
亚德诺 - ADI 转换器光电二极管
页数 文件大小 规格书
24页 594K
描述
Quad-Channel Isolators with Integrated DC-to-DC Converter

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ADUM6403ARWZ 数据手册

 浏览型号ADUM6403ARWZ的Datasheet PDF文件第4页浏览型号ADUM6403ARWZ的Datasheet PDF文件第5页浏览型号ADUM6403ARWZ的Datasheet PDF文件第6页浏览型号ADUM6403ARWZ的Datasheet PDF文件第8页浏览型号ADUM6403ARWZ的Datasheet PDF文件第9页浏览型号ADUM6403ARWZ的Datasheet PDF文件第10页 
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404  
Table 11. DC-to-DC Converter Dynamic Specifications  
2 Mbps—A Grade, B Grade, C Grade  
25 Mbps—C Grade  
Parameter  
Symbol  
Min  
Typ  
Max  
Min  
Typ  
Max  
Unit  
Test Conditions  
No VISO load  
No VISO load  
No VISO load  
No VISO load  
No VISO load  
SUPPLY CURRENT  
ADuM6400  
IDD1  
9
100  
9
100  
9
100  
9
100  
9
100  
43  
93  
44  
92  
45  
91  
46  
89  
47  
88  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IISO (LOAD)  
IDD1  
IISO (LOAD)  
IDD1  
IISO (LOAD)  
IDD1  
IISO (LOAD)  
IDD1  
ADuM6401  
ADuM6402  
ADuM6403  
ADuM6404  
IISO (LOAD)  
Table 12. Switching Specifications  
A Grade  
Typ  
C Grade  
Typ  
Parameter  
Symbol  
Min  
Max  
Min  
Max  
Unit  
Test Conditions  
SWITCHING SPECIFICATIONS  
Data Rate  
Propagation Delay  
Pulse Width Distortion  
Change vs. Temperature  
Pulse Width  
1
100  
40  
25  
60  
6
Mbps  
ns  
ns  
ps/°C  
ns  
ns  
Within PWD limit  
50% input to 50% output  
|tPLH − tPHL|  
tPHL, tPLH  
PWD  
60  
45  
5
PW  
tPSK  
1000  
40  
Within PWD limit  
Between any two units  
Propagation Delay Skew  
Channel Matching  
Codirectional1  
50  
15  
tPSKCD  
tPSKOD  
50  
50  
6
15  
ns  
ns  
Opposing Directional2  
1
7
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.  
2 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.  
Table 13. Input and Output Characteristics  
Parameter  
Symbol Min  
Typ  
Max  
Unit  
Test Conditions  
DC SPECIFICATIONS  
Logic High Input Threshold  
Logic Low Input Threshold  
Logic High Output Voltages  
VIH  
VIL  
VOH  
0.7 VISO or 0.7 VDD1  
V
V
V
V
0.3 VISO or 0.3 VDD1  
VDD1 − 0.2, VISO − 0.2  
VDD1 − 0.5 or  
VDD1 or VISO  
VDD1 − 0.2 or  
IOx = −20 μA, VIx = VIxH  
IOx = −4 mA, VIx = VIxH  
VISO − 0.5  
VISO − 0.2  
Logic Low Output Voltages  
VOL  
0.0  
0.0  
0.1  
0.4  
V
V
IOx = 20 μA, VIx = VIxL  
IOx = 4 mA, VIx = VIxL  
VDD1, VDDL, VISO supply  
Undervoltage Lockout  
Positive Going Threshold  
Negative Going Threshold  
Hysterisis  
Input Currents per Channel  
AC SPECIFICATIONS  
Output Rise/Fall Time  
Common-Mode Transient  
Immunity1  
VUV+  
VUV−  
VUVH  
II  
2.7  
2.4  
0.3  
+0.01  
V
V
V
μA  
−10  
25  
+10  
0 V ≤ VIx ≤ VDDx  
10% to 90%  
tR/tF  
|CM|  
2.5  
35  
ns  
kV/μs VIx = VDD1 or VISO, VCM = 1000 V,  
transient magnitude = 800 V  
Refresh Rate  
fr  
1.0  
Mbps  
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 × VDD1 or 0.8 × VISO for a high input or VO < 0.8 × VDD1 or 0.8 × VISO for a  
low input. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.  
Rev. 0 | Page 7 of 24  
 
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