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ADUM5400CRWZ2

更新时间： 2022-04-23 23:00:11
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
21页 381K
描述
Quad-Channel Isolator with Integrated DC-to-DC Converter

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ADUM5400CRWZ2 数据手册

 浏览型号ADUM5400CRWZ2的Datasheet PDF文件第1页浏览型号ADUM5400CRWZ2的Datasheet PDF文件第2页浏览型号ADUM5400CRWZ2的Datasheet PDF文件第4页浏览型号ADUM5400CRWZ2的Datasheet PDF文件第5页浏览型号ADUM5400CRWZ2的Datasheet PDF文件第6页浏览型号ADUM5400CRWZ2的Datasheet PDF文件第7页 
Preliminary Technical Data  
SPECIFICATIONS  
ADuM5400  
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY  
4.5 V ≤ VDD1 ≤ 5.5 V, VSEL = VISO; all voltages are relative to their respective ground. All minimum/maximum specifications apply over the  
entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = 5.0 V, VSEL = VISO = 5.0 V.  
Table 1.  
Parameter  
Symbol  
Min  
Typ  
Max  
5.4  
5
Unit  
Test Conditions/Comments  
DC-TO-DC CONVERTER POWER SUPPLY  
Setpoint  
Line Regulation  
Load Regulation  
Output Ripple  
VISO  
4.7  
5.0  
1
1
V
IISO = 0 mA  
IISO = 50 mA, VDD1 = 4.5 V to 5.5 V  
IISO = 10 mA to 90 mA  
VISO(LINE)  
VISO(LOAD)  
VISO(RIP)  
mV/V  
%
mV p-p  
75  
20 MHz bandwidth, CBO = 0.1 μF║10 μF,  
IISO = 90 mA  
Output Noise  
VISO(N)  
200  
mV p-p  
20 MHz bandwidth, CBO = 0.1 μF║10 μF,  
IISO = 90 mA  
Switching Frequency  
fOSC  
fPWM  
180  
625  
MHz  
kHz  
Pulse-Width Modulation Frequency  
iCoupler DATA CHANNELS  
DC to 2 Mbps Data Rate1  
Maximum Output Supply Current2  
Efficiency at Maximum Output Supply  
Current3  
IDD1 Supply Current, No VISO Load  
25 Mbps Data Rate (CRWZ Grade Only)  
IDD1 Supply Current, No VISO Load  
ADuM5400  
IISO(MAX)  
100  
mA  
%
f ≤ 1 MHz, VISO > 4.5 V  
IISO = IISO(2,MAX), f ≤ 1 MHz  
34  
19  
IDD1(Q)  
30  
mA  
IISO = 0 mA, f ≤ 1 MHz  
IDD1(D)  
64  
mA  
IISO = 0 mA, CL = 15 pF, f = 12.5 MHz  
Available VISO Supply Current4  
ADuM5400  
IDD1 Supply Current, Full VISO Load  
I/O Input Currents  
IISO(LOAD)  
89  
290  
+0.01 +20  
mA  
mA  
μA  
V
CL = 15 pF, f = 12.5 MHz  
CL = 0 pF, f = 0 MHz, VDD = 5 V, IISO = 100 mA  
IDD1(MAX)  
IIA, IIB, IIC, IID  
VIH  
−20  
0.7 × VISO,  
0.7 × VIDD1  
Logic High Input Threshold  
Logic Low Input Threshold  
Logic High Output Voltages  
VIL  
0.3 × VISO,  
0.3 ×  
VIDD1  
V
VOAH, VOBH  
VOCH, VODH  
,
VDD1 − 0.3, 5.0  
VISO − 0.3  
VDD1 − 0.5, 4.8  
VISO − 0.3  
V
V
V
V
I
I
I
Ox = −20 μA, VIx = VIxH  
Ox = −4 mA, VIx = VIxH  
Ox = 20 μA, VIx = VIxL  
Logic Low Output Voltages  
VOAL, VOBL  
VOCL, VODL  
,
0.0  
0.1  
0.4  
0.0  
IOx = 4 mA, VIx = VIxL  
AC SPECIFICATIONS  
ADuM5400ARWZ  
Minimum Pulse Width  
Maximum Data Rate  
Propagation Delay  
Pulse Width Distortion, |tPLH − tPHL  
Propagation Delay Skew  
Channel-to-Channel Matching  
ADuM5400CRWZ  
PW  
1000  
ns  
Mbps  
ns  
ns  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
1
tPHL, tPLH  
PWD  
tPSK  
55  
100  
40  
50  
|
tPSKCD/tPSKOD  
50  
ns  
Minimum Pulse Width  
Maximum Data Rate  
Propagation Delay  
Pulse Width Distortion, |tPLH − tPHL  
Change vs. Temperature  
Propagation Delay Skew  
PW  
40  
ns  
Mbps  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
25  
tPHL, tPLH  
PWD  
45  
60  
6
|
ns  
5
ps/°C  
ns  
ns  
tPSK  
tPSKCD  
15  
6
Channel-to-Channel Matching,  
Rev. PrA | Page 3 of 21  
1234567...21

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