Preliminary Technical Data
ADuM5400
ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
3.0 V ≤ VDD1 ≤ 3.6 V, VSEL = GNDISO; all voltages are relative to their respective ground. All minimum/maximum specifications apply over
the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = 3.3 V, VISO = 3.3 V,
VSEL = GNDISO.
Table 2.
Parameter
DC-TO-DC CONVERTER POWER SUPPLY
Setpoint
Line Regulation
Load Regulation
Symbol
Min
Typ
Max
3.6
5
Unit
Test Conditions/Comments
VISO
3.0
3.3
1
1
V
IISO = 0 mA
IISO = 37.5 mA, VDD1 = 3.0 V to 3.6 V
IISO = 6 mA to 54 mA
VISO(LINE)
VISO(LOAD)
VISO(RIP)
mV/V
%
mV p-p
Output Ripple
50
20 MHz bandwidth, CBO = 0.1 μF║10 μF,
IISO = 54 mA
Output Noise
VISO(N)
130
mV p-p
20 MHz bandwidth, CBO = 0.1 μF║10 μF,
IISO = 54 mA
Switching Frequency
Pulse-Width Modulation Frequency
fOSC
fPWM
180
625
MHz
kHz
iCoupler DATA CHANNELS
DC to 2 Mbps Data Rate1
Maximum Output Supply Current2
Efficiency at Maximum Output Supply
Current3
IDD1 Supply Current, No VISO Load
25 Mbps Data Rate (CRWZ Grade Only)
IDD1 Supply Current, No VISO Load
ADuM5400
IISO(MAX)
60
mA
%
f ≤ 1 MHz, VISO > 3.0 V
IISO = IISO(2,max), f ≤ 1 MHz
36
14
IDD1(Q)
20
mA
IISO = 0 mA, f ≤ 1 MHz
IDD1(D)
41
mA
IISO = 0 mA, CL = 15 pF, f = 12.5 MHz
Available VISO Supply Current4
ADuM5400
IDD1 Supply Current, Full VISO Load
I/O Input Currents
IISO(LOAD)
43
175
+0.01
mA
mA
μA
V
CL = 15 pF, f = 12.5 MHz
CL = 0 pF, f = 0 MHz, VDD = 3.3 V, IISO = 60 mA
IDD1(MAX)
IIA, IIB, IIC, IID
VIH
−10
0.7 × VISO,
0.7 × VIDD1
+10
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
VIL
0.3 × VISO,
0.3 × VIDD1
V
V
V
V
V
VOAH, VOBH
VOCH, VODH
,
VDD1 − 0.2, 5.0
VISO − 0.2
VDD1 − 0.5, 4.8
V1SO − 0.5
I
I
I
Ox = −20 μA, VIx = VIxH
Ox = −4 mA, VIx = VIxH
Ox = 20 μA, VIx = VIxL
Logic Low Output Voltages
VOAL, VOBL
VOCL, VODL
,
0.0
0.1
0.4
0.0
IOx = 4 mA, VIx = VIxL
AC SPECIFICATIONS
ADuM5400ARWZ
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |tPLH − tPHL
Propagation Delay Skew
Channel-to-Channel Matching
ADuM5400CRWZ
PW
1000
ns
Mbps
ns
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
tPHL, tPLH
PWD
tPSK
60
100
40
50
|
tPSKCD/tPSKOD
50
ns
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew
Channel-to-Channel Matching,
Codirectional Channels
PW
40
ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
25
tPHL, tPLH
PWD
45
60
6
|
ns
5
ps/°C
ns
ns
tPSK
tPSKCD
45
6
Rev. PrA | Page 5 of 21
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