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ADUM5240BRZ

更新时间： 2024-02-23 14:11:13
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
10页 142K
描述
Dual-Channel Isolators with Integrated DC/DC Converter, 50 mW

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ADUM5240BRZ 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOIC-8针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.64
接口集成电路类型：INTERFACE CIRCUITJESD-30 代码：R-PDSO-G8
JESD-609代码：e3长度：4.9 mm
湿度敏感等级：1功能数量：1
端子数量：8最高工作温度：105 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.75 mm
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：3.9 mmBase Number Matches：1

ADUM5240BRZ 数据手册

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Preliminary Technical Data  
ADuM5240/ADuM5241/ADuM5242  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions  
AC SPECIFICATIONS  
Minimum Pulse Width5  
Maximum Data Rate6  
PW  
100  
ns  
Mbps  
ns  
ns  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
10  
25  
Propagation Delay7  
tPHL, tPLH  
PWD  
tPSK  
70  
3
45  
3
7
Pulse-Width Distortion, |tPLH − tPHL  
Propagation Delay Skew8  
Channel-to-Channel Matching,  
Codirectional Channels9  
|
tPSKCD  
ns  
Channel-to-Channel Matching,  
tPSKCD  
15  
ns  
CL = 15 pF, CMOS signal levels  
Opposing-Directional Channels10  
Ripple11  
200  
50  
50  
2.5  
35  
mVP-P  
ns  
ns  
ns  
kV/μs  
Enable Time12  
TENABLE  
TDISABLE  
tR/tF  
Disable Time12  
Output Rise/Fall Time (10% to 90%)  
Common-Mode Transient Immunity  
at Logic High Output  
Common-Mode Transient Immunity  
at Logic Low Output  
Refresh Frequency  
CL = 15 pF, CMOS signal levels  
VIx = VDD, VISO, VCM = 1000 V,  
transient magnitude = 800 V  
VIx = 0 V, V = 1000 V,  
transient magnitude = 800 V  
|CMH|  
25  
25  
|CML|  
fr  
35  
kV/μs  
MHz  
1.0  
1 All voltages are relative to their respective ground.  
2 Supply current values are specified with no load present on the digital outputs.  
3 Supply current values are specified with no load present on the digital outputs.  
4 Enable/disable threshold is the voltage at which the internal DC/DC converter is enabled/disabled.  
5 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.  
6 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.  
7 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is  
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.  
8 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output  
load within the recommended operating conditions.  
9 Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads.  
10 Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads.  
11 Ripple occurs at frequency corresponding to the input signal data rate or the refresh frequency for data rates below 1Mbps.  
12 Enable time is the duration from when input supply voltage rises above the enable threshold to when the internal DC/DC converter starts charging an external load.  
Disable time is the duration from when the input supply voltage drops below the disable threshold to when the internal DC/DC converter stops charging an external  
load  
PACKAGE CHARACTERISTICS  
Table 2.  
Parameter  
Symbol  
RI-O  
CI-O  
Min  
Typ  
1012  
1.0  
Max  
Unit  
Ω
pF  
Test Conditions  
Resistance (Input-Output)  
Capacitance (Input-Output)  
Input Capacitance  
f = 1 MHz  
CI  
4.0  
pF  
IC Junction-to-Air Thermal Resistance  
θJA  
150  
°C/W  
Rev. PrN | Page 3 of 10  
1234567...10

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