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ADUM4402WARWZ

更新时间： 2024-02-19 16:29:57
品牌 Logo 应用领域
亚德诺 - ADI 接口集成电路
页数 文件大小 规格书
20页 382K
描述
5 kV RMS Quad-Channel Digital Isolators

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ADUM4402WARWZ 技术参数

Source Url Status Check Date：2013-05-01 14:56:51.001是否无铅： 含铅
是否Rohs认证： 符合生命周期：Active
包装说明：,针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8543.70.99.60风险等级：5.56
接口集成电路类型：INTERFACE CIRCUITBase Number Matches：1

ADUM4402WARWZ 数据手册

 浏览型号ADUM4402WARWZ的Datasheet PDF文件第2页浏览型号ADUM4402WARWZ的Datasheet PDF文件第3页浏览型号ADUM4402WARWZ的Datasheet PDF文件第4页浏览型号ADUM4402WARWZ的Datasheet PDF文件第6页浏览型号ADUM4402WARWZ的Datasheet PDF文件第7页浏览型号ADUM4402WARWZ的Datasheet PDF文件第8页 
Automotive Products  
ADuM4400W/ADuM4401W/ADuM4402W  
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3.3 V OPERATION  
All typical specifications are at TA = 25°C, VDD1 = 5 V, V DD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended  
operation range: 4.5 V ≤ VDD1 ≤ 5.5 V, 3.135 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ 125°C, unless otherwise noted. Switching specifications  
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.  
Table 7.  
WA Grade  
Typ  
WB Grade  
Typ  
Parameter  
Symbol  
Min  
50  
Max  
Min  
20  
Max  
Unit  
Test Conditions/Comments  
SWITCHING SPECIFICATIONS  
Data Rate  
Propagation Delay  
Pulse Width Distortion  
Change vs. Temperature  
Pulse Width  
Propagation Delay Skew  
Channel Matching  
Codirectional  
1
100  
40  
10  
42  
3.5  
Mbps  
ns  
ns  
Within PWD limit  
50% input to 50% output  
|tPLH − tPHL|  
tPHL, tPLH  
PWD  
70  
11  
30  
5
ps/°C  
ns  
PW  
tPSK  
1000  
100  
Within PWD limit  
50  
22  
ns  
Between any two units  
tPSKCD  
tPSKOD  
50  
50  
3.5  
6
ns  
ns  
Opposing-Direction  
Table 8.  
1 Mbps—WA, WB Grades  
10 Mbps—WB Grade  
Parameter  
Symbol  
Min  
Typ  
Max  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
SUPPLY CURRENT  
ADuM4400W  
IDD1  
IDD2  
IDD1  
IDD2  
IDD1  
IDD2  
2.9  
0.7  
2.5  
0.9  
2.0  
1.2  
3.5  
1.4  
3.2  
1.6  
2.8  
1.8  
9.0  
1.8  
7.4  
2.5  
6.0  
3.3  
11.6  
2.6  
10.6  
3.3  
7.5  
4.4  
mA  
mA  
mA  
mA  
mA  
mA  
ADuM4401W  
ADuM4402W  
Table 9. For All Models  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
DC SPECIFICATIONS  
5 V Logic High Input Threshold  
3.3 V Logic High Input Threshold  
5 V Logic Low Input Threshold  
3.3 V Logic Low Input Threshold  
Logic High Output Voltage  
VIH  
VIH  
VIL  
VIL  
VOH  
2.0  
1.6  
V
V
V
V
V
V
V
V
0.8  
0.4  
VDDx − 0.1  
VDDx − 0.4  
3.0  
2.8  
0.0  
0.04  
0.2  
+0.01  
−3  
+0.01  
IOx = −20 µA, VIx = VIxH  
IOx = −4 mA, VIx = VIxH  
IOx = 20 µA, VIx = VIxL  
IOx = 400 µA, VIx = VIxL  
IOx = 4 mA, VIx = VIxL  
0 V ≤ VIx ≤ VDDx  
Logic Low Output Voltage  
VOL  
0.1  
0.1  
0.4  
+10  
V
Input Current per Channel  
VEx Input Pull-up Current  
II  
IPU  
IOZ  
−10  
−10  
−10  
µA  
µA  
µA  
VEx = 0 V  
Tristate Leakage Current per Channel  
Supply Current per Channel  
Quiescent Input Supply Current  
Quiescent Output Supply Current  
Dynamic Input Supply Current  
Dynamic Output Supply Current  
AC SPECIFICATIONS  
+10  
IDDI(Q)  
IDDO(Q)  
IDDI(D)  
IDDO(D)  
0.57  
0.29  
0.20  
0.03  
0.83  
0.27  
mA  
mA  
mA/Mbps  
mA/Mbps  
All data inputs at logic low  
All data inputs at logic low  
Output Rise/Fall Time  
tR/tF  
3
ns  
10% to 90%  
Common-Mode Transient Immunity1  
|CM|  
25  
35  
kV/µs  
VIx = VDDx, VCM = 1000 V,  
transient magnitude = 800 V  
Output Disable Propagation Delay  
Output Enable Propagation Delay  
Refresh Rate  
tPHZ, tPLH  
tPZH, tPZL  
fr  
6
6
1.0  
8
8
ns  
ns  
Mbps  
High/low-to-high impedance  
High impedance-to-high/low  
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOx > 0.8 VDD. The common-mode voltage slew rates apply to both  
rising and falling common-mode voltage edges.  
Rev. A | Page 5 of 20  
 
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