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ADUM3301WBRWZ PDF预览

ADUM3301WBRWZ

更新时间: 2024-01-31 22:26:41
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管接口集成电路
页数 文件大小 规格书
20页 454K
描述
Triple-Channel, Digital Isolator, Enhanced System-Level ESD Reliability (2/1 channel directionality)

ADUM3301WBRWZ 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active包装说明:SOP,
针数:16Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8543.70.99.60
风险等级:5.57接口集成电路类型:INTERFACE CIRCUIT
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:10.3 mm湿度敏感等级:3
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260座面最大高度:2.65 mm
最大供电电压:5.5 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:7.5 mm
Base Number Matches:1

ADUM3301WBRWZ 数据手册

 浏览型号ADUM3301WBRWZ的Datasheet PDF文件第1页浏览型号ADUM3301WBRWZ的Datasheet PDF文件第2页浏览型号ADUM3301WBRWZ的Datasheet PDF文件第3页浏览型号ADUM3301WBRWZ的Datasheet PDF文件第5页浏览型号ADUM3301WBRWZ的Datasheet PDF文件第6页浏览型号ADUM3301WBRWZ的Datasheet PDF文件第7页 
ADuM3300/ADuM3301  
Data Sheet  
Parameter  
Symbol  
Min  
Typ  
Max Unit  
Test Conditions  
ADuM3300BRWZ/ADuM3301BRWZ  
Minimum Pulse Width2  
Maximum Data Rate3  
PW  
100 ns  
Mbps  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
10  
20  
Propagation Delay4  
tPHL, tPLH  
PWD  
32  
5
50  
3
ns  
ns  
4
Pulse Width Distortion, |tPLH − tPHL  
Change vs. Temperature  
Propagation Delay Skew5  
Channel-to-Channel Matching,  
Codirectional Channels6  
|
ps/°C  
ns  
ns  
tPSK  
tPSKCD  
15  
3
Channel-to-Channel Matching,  
tPSKOD  
6
ns  
CL = 15 pF, CMOS signal levels  
Opposing-Directional Channels6  
ADuM3300CRWZ/ADuM3301CRWZ  
Minimum Pulse Width2  
PW  
8.3  
120  
27  
0.5  
3
11.1 ns  
Mbps  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
Maximum Data Rate3  
Propagation Delay4  
Pulse Width Distortion, |tPLH − tPHL  
Change vs. Temperature  
Propagation Delay Skew5  
90  
18  
tPHL, tPLH  
PWD  
32  
2
4
|
ns  
ps/°C  
ns  
tPSK  
tPSKCD  
10  
2
Channel-to-Channel Matching,  
Codirectional Channels6  
ns  
Channel-to-Channel Matching,  
tPSKOD  
5
ns  
CL = 15 pF, CMOS signal levels  
Opposing-Directional Channels6  
For All Models  
Output Disable Propagation Delay  
(High/Low-to-High Impedance)  
Output Enable Propagation Delay  
(High Impedance-to-High/Low)  
Output Rise/Fall Time (10% to 90%)  
Common-Mode Transient Immunity  
at Logic High Output7  
tPHZ, tPLH  
tPZH, tPZL  
6
6
8
8
ns  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
VIx = VDD1 or VDD2, VCM = 1000 V,  
transient magnitude = 800 V  
VIx = 0 V, VCM = 1000 V,  
tR/tF  
|CMH|  
2.5  
35  
ns  
kV/µs  
25  
25  
Common-Mode Transient Immunity  
at Logic Low Output7  
|CML|  
35  
kV/µs  
transient magnitude = 800 V  
Refresh Rate  
fr  
1.2  
Mbps  
Input Dynamic Supply Current per Channel8  
Output Dynamic Supply Current per Channel8  
IDDI (D)  
IDDO (D)  
0.20  
0.05  
mA/Mbps  
mA/Mbps  
1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load  
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.  
See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through  
Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM3300/ADuM3301 channel configurations.  
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.  
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.  
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is  
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.  
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load  
within the recommended operating conditions.  
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of  
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with  
inputs on opposing sides of the isolation barrier.  
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate  
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient  
magnitude is the range over which the common mode is slewed.  
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information  
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current  
for a given data rate.  
Rev. E | Page 4 of 20  
 

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