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ADUM3223CRZ

更新时间： 2024-02-01 02:50:31
品牌 Logo 应用领域
亚德诺 - ADI 外围驱动器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
20页 409K
描述
Isolated Precision Half-Bridge Driver

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ADUM3223CRZ 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active包装说明：SOIC-16
针数：16Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：2.37其他特性：OTHER SUPPLY VOLTAGE= 4.5V TO 18V
内置保护：THERMAL; UNDER VOLTAGE接口集成电路类型：HALF BRIDGE BASED PERIPHERAL DRIVER
JESD-30 代码：R-PDSO-G16JESD-609代码：e3
长度：9.9 mm湿度敏感等级：3
功能数量：2端子数量：16
最高工作温度：125 °C最低工作温度：-40 °C
标称输出峰值电流：4 A封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
座面最大高度：1.75 mm最大供电电压：5.5 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES温度等级：AUTOMOTIVE
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：3.9 mm

ADUM3223CRZ 数据手册

 浏览型号ADUM3223CRZ的Datasheet PDF文件第1页浏览型号ADUM3223CRZ的Datasheet PDF文件第2页浏览型号ADUM3223CRZ的Datasheet PDF文件第3页浏览型号ADUM3223CRZ的Datasheet PDF文件第5页浏览型号ADUM3223CRZ的Datasheet PDF文件第6页浏览型号ADUM3223CRZ的Datasheet PDF文件第7页 
ADuM3223/ADuM4223  
Data Sheet  
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION  
All voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 18 V, unless stated otherwise. All minimum/  
maximum specifications apply over TJ = −40°C to 125°C. All typical specifications are at TJ = 25°C, VDD1 = 3.3 V, VDD2 = 12 V. Switching  
specifications are tested with CMOS signal levels.  
Table 2.  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions  
DC SPECIFICATIONS  
Input Supply Current, Quiescent  
Output Supply Current, Per Channel, Quiescent  
Supply Current at 1 MHz  
VDD1 Supply Current  
VDDA/VDDB Supply Current  
Input Currents  
Logic High Input Threshold  
Logic Low Input Threshold  
Logic High Output Voltages  
Logic Low Output Voltages  
Undervoltage Lockout, VDD2 Supply  
Positive Going Threshold  
Negative Going Threshold  
Hysteresis  
IDDI(Q)  
IDDO(Q)  
0.87  
2.3  
1.4  
3.2  
mA  
mA  
IDD1(Q)  
IDDA/IDDB(Q)  
IIA, IIB  
VIH  
VIL  
1.1  
5.6  
+0.01  
1.5  
8.0  
+10  
mA  
mA  
µA  
V
V
V
Up to 1 MHz, no load  
Up to 1 MHz, no load  
0 ≤ VIA, VIB ≤ VDD1  
−10  
0.7 × VDD1  
0.3 × VDD1  
0.15  
VOAH, VOBH  
VOAL, VOBL  
VDD2 – 0.1  
VDD2  
0.0  
IOx = −20 mA, VIx = VIxH  
IOx = +20 mA, VIx = VIxL  
V
VDD2UV+  
VDD2UV−  
VDD2UVH  
VDD2UV+  
VDD2UV−  
VDD2UVH  
VDD2UV+  
VDD2UV−  
VDD2UVH  
4.1  
3.6  
0.5  
6.9  
6.2  
0.7  
10.5  
9.6  
0.9  
4.0  
1.1  
0.6  
4.4  
V
V
V
V
V
V
V
V
V
A
Ω
Ω
A-grade  
A-grade  
A-grade  
B-grade  
B-grade  
B-grade  
C-grade  
C-grade  
C-grade  
3.2  
5.7  
8.9  
Positive Going Threshold  
Negative Going Threshold  
Hysteresis  
Positive Going Threshold  
Negative Going Threshold  
Hysteresis  
7.4  
11.1  
Output Short-Circuit Pulsed Current1  
Output Pulsed Source Resistance  
Output Pulsed Sink Resistance  
SWITCHING SPECIFICATIONS  
Pulse Width2  
Maximum Data Rate3  
Propagation Delay4  
IOA(SC), IOB(SC) 2.0  
ROA, ROB  
ROA, ROB  
VDD2 = 12 V  
VDD2 = 12 V  
VDD2 = 12 V  
PW  
50  
1
ns  
MHz  
CL = 2 nF, VDD2 = 12 V  
CL = 2 nF, VDD2 = 12 V  
tDHL, tDLH  
tDHL, tDLH  
tPSK  
30  
32  
42  
46  
54  
60  
12  
5
ns  
CL = 2 nF, VDD2 = 12 V, see Figure 20  
CL = 2 nF, VDD2 = 4.5 V, see Figure 20  
CL = 2 nF, VDD2 = 12 V, see Figure 20  
CL = 2 nF, VDD2 = 12 V, see Figure 20  
CL = 2 nF, VDD2 = 4.5 V, see Figure 20  
CL = 2 nF, VDD2 = 12 V, see Figure 20  
VDD2 = 12 V  
ADuM3223A/ADuM4223A  
Propagation Delay Skew5  
Channel-to-Channel Matching6  
ns  
ns  
tPSKCD  
tPSKCD  
tR/tF  
1
ns  
1
7
ns  
Output Rise/Fall Time (10% to 90%)  
Dynamic Input Supply Current Per Channel  
Dynamic Output Supply Current Per Channel  
Refresh Rate  
6
12  
22  
ns  
IDDI(D)  
IDDO(D)  
fr  
0.05  
1.65  
1.1  
mA/Mbps  
mA/Mbps  
Mbps  
VDD2 = 12 V  
1 Short-circuit duration less than 1 µs. Average power must conform to the limit shown under the Absolute Maximum Ratings.  
2 The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed.  
3 The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed.  
4 tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% level of the VOx signal. tDHL propagation delay is  
measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. See Figure 20 for waveforms of propagation delay  
parameters.  
5 tPSK is the magnitude of the worst-case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output  
load within the recommended operating conditions. See Figure 20 for waveforms of propagation delay parameters.  
6 Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels.  
Rev. 0| Page 4 of 20  
 
 
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