Data Sheet
ADuM3220/ADuM3221
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 18 V, unless stated otherwise. All minimum/
maximum specifications apply over TJ = −40°C to +125°C. All typical specifications are at TJ = 25°C, VDD1 = 5 V, VDD2 = 10 V. Switching
specifications are tested with CMOS signal levels.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
DC SPECIFICATIONS
Input Supply Current, Two Channels, Quiescent
IDDI(Q)
1.2
4.7
1.5
10
mA
mA
Output Supply Current, Two Channels, Quiescent IDDO(Q)
Total Supply Current, Two Channels1
DC to 1 MHz
VDD1 Supply Current
VDD2 Supply Current
Input Currents
IDD1(Q)
IDD2(Q)
IIA, IIB
VIH
VIL
1.4
11
1.7
17
mA
mA
µA
V
V
V
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
0 V ≤ VIA, VIB ≤ VDD1
−10
0.7 × VDD1
+0.01 +10
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
Undervoltage Lockout, VDD2 Supply
ADuM3220A/ADuM3221A
Positive-Going Threshold
Negative-Going Threshold
Hysteresis
ADuM3220B/ADuM3221B
Positive-Going Threshold
Negative-Going Threshold
Hysteresis
Output Short-Circuit Pulsed Current2
Output Pulsed Source Resistance
Output Pulsed Sink Resistance
SWITCHING SPECIFICATIONS
Pulse Width3
Data Rate4
Propagation Delay5
0.3 × VDD1
0.15
VOAH, VOBH
VOAL, VOBL
VDD2 − 0.1 VDD2
0.0
IOx = −20 mA, VIx = VIxH
IOx = +20 mA, VIx = VIxL
V
VDD2UV+
VDD2UV−
VDD2UVH
4.1
3.7
0.4
4.4
7.5
V
V
V
3.2
6.0
VDD2UV+
VDD2UV−
VDD2UVH
IOA(SC), IOB(SC) 2.0
ROA, ROB
ROA, ROB
7.0
6.5
0.5
4.0
1.3
0.9
V
V
V
A
Ω
Ω
VDD2 = 10 V
VDD2 = 10 V
VDD2 = 10 V
0.3
0.3
3.0
3.0
PW
50
ns
MHz
ns
ns
ns
ns
ns
ns
ns
CL = 2 nF, VDD2 = 10 V
CL = 2 nF, VDD2 = 10 V
1
tDLH, tDHL
tDLH, tDHL
tPSK
tPSKCD
tPSKCD
tR/tF
35
36
45
50
60
68
12
5
7
25
28
CL = 2 nF, VDD2 = 10 V; see Figure 20
CL = 2 nF, VDD2 = 4.5 V; see Figure 20
CL = 2 nF, VDD2 = 10 V; see Figure 20
CL = 2 nF, VDD2 = 10 V; see Figure 20
CL = 2 nF, VDD2 = 4.5 V; see Figure 20
CL = 2 nF, VDD2 = 10 V; see Figure 20
CL = 2 nF, VDD2 = 4.5 V; see Figure 20
Propagation Delay Skew6
Channel-to-Channel Matching7
1
1
Output Rise/Fall Time (10% to 90%)
14
14
20
22
0.05
1.5
1.2
tR/tF
Dynamic Input Supply Current per Channel
Dynamic Output Supply Current per Channel
Refresh Rate
IDDI(D)
IDDO(D)
fr
mA/Mbps VDD2 = 10 V
mA/Mbps VDD2 = 10 V
Mbps
1 The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 9 and Figure 10 for total VDD1 and VDD2 supply currents as a function of frequency.
2 Short-circuit duration less than 1 µs. Average power must conform to the limit shown in the Absolute Maximum Ratings section.
3 The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed.
5 tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% threshold of the VOx signal. tDHL propagation
delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. See Figure 20 for waveforms of propagation
delay parameters.
6 tPSK is the magnitude of the worst-case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions. See Figure 20 for waveforms of propagation delay parameters.
7 Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
Rev. C | Page 3 of 16
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