Data Sheet
ADuM3151/ADuM3152/ADuM3153
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All typical specifications are at TA = 25°C and VDD1 = VDD2 = 5 V. Minimum and maximum specifications apply over the entire
recommended operation range: 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching
specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 1. Switching Specifications
A Grade
Typ
B Grade
Typ
Parameter
Symbol
Min
Max
Min
Max
Unit
Test Conditions/Comments
MCLK, MO, SO
SPI Clock Rate
SPIMCLK
DRFAST
tPHL, tPLH
PW
1
2
25
17
34
14
MHz
Mbps
ns
Data Rate Fast (MO, SO)
Propagation Delay
Pulse Width
Within PWD limit
50% input to 50% output
Within PWD limit
12
100
12.5
ns
Pulse Width Distortion
Codirectional Channel Matching1
Jitter, High Speed
MSS
PWD
tPSKCD
JHS
3
3
2
2
ns
ns
ns
|tPLH − tPHL|
1
1
Data Rate Fast
Propagation Delay
Pulse Width
Pulse Width Distortion
Setup Time2
DRFAST
tPHL, tPLH
PW
PWD
MSSSETUP
JHS
2
25
34
25
Mbps
ns
ns
ns
ns
Within PWD limit
50% input to 50% output
Within PWD limit
21
21
100
1.5
12.5
10
3
3
|tPLH − tPHL|
Jitter, High Speed
VIA, VIB, VIC
1
1
ns
Data Rate Slow
Propagation Delay
Pulse Width
DRSLOW
tPHL, tPLH
PW
250
2.6
250
2.6
kbps
µs
µs
Within PWD limit
50% input to 50% output
Within PWD limit
0.1
4
0.1
4
Jitter, Low Speed
VIx3 Minimum Input Skew4
JLS
tVIx SKEW
2.5
2.5
µs
ns
3
10
10
1 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
2
MSS
MSS
The
signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that
reaches the output
MSS
ahead of another fast signal, set up
prior to the competing signal by different times depending on speed grade.
3 VIx = VIA, VIB, or VIC.
4 An internal asynchronous clock not available to users samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the
leading pulse must be at least 1 tVIx SKEW time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.
Table 2. Supply Current
1 MHz, A Grade
17 MHz, B Grade
Device Number
Symbol
IDD1
IDD2
Min
Typ
4.0
6.0
4.8
6.5
4.0
6.0
Max
Min
Typ
14.0
13.5
14.0
14.0
14.0
13.3
Max
Unit
mA
mA
mA
mA
mA
mA
Test Conditions/Comments
CL = 0 pF, low speed channels
CL = 0 pF, low speed channels
CL = 0 pF, low speed channels
CL = 0 pF, low speed channels
CL = 0 pF, low speed channels
CL = 0 pF, low speed channels
ADuM3151
8.5
10.5
8
10.5
6.5
12
22
23
ADuM3152
ADuM3153
IDD1
IDD2
21.5
22.5
21.5
21
IDD1
IDD2
Rev. B | Page 3 of 22