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ADUM221N

更新时间: 2023-09-23 06:49:11
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
23页 481K
描述
可靠的 5.0 kV rms 双通道数字隔离器、1 个反向通道和 7.8mm 爬电距离

ADUM221N 数据手册

 浏览型号ADUM221N的Datasheet PDF文件第1页浏览型号ADUM221N的Datasheet PDF文件第2页浏览型号ADUM221N的Datasheet PDF文件第4页浏览型号ADUM221N的Datasheet PDF文件第5页浏览型号ADUM221N的Datasheet PDF文件第6页浏览型号ADUM221N的Datasheet PDF文件第7页 
Data Sheet  
ADuM220N/ADuM221N/ADuM225N/ADuM226N  
SPECIFICATIONS  
ELECTRICAL CHARACTERISTICS—5 V OPERATION  
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. M inimum/maximum specifications apply over the entire recommended  
operation range of 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications  
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.  
Table 1.  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
SWITCHING SPECIFICATIONS  
Pulse Width  
PW  
6.6  
ns  
Within pulse width distortion (PWD)  
limit  
Data Rate  
150  
4.8  
Mbps  
ns  
ns  
ps/°C  
ns  
Within PWD limit  
50% input to 50% output  
|tPLH − tPHL|  
Propagation Delay  
Pulse Width Distortion  
Change vs. Temperature  
Propagation Delay Skew  
tPHL, tPLH  
PWD  
7.2  
0.5  
1.5  
13  
3
tPSK  
6.0  
Between any two units at the  
same temperature, voltage, and load  
Channel Matching  
Codirectional  
Opposing Direction  
Jitter  
tPSKCD  
tPSKOD  
0.5  
0.5  
380  
55  
3.0  
3.0  
ns  
ns  
ps p-p  
ps rms  
See the Jitter Measurement section  
See the Jitter Measurement section  
DC SPECIFICATIONS  
Input Threshold  
Logic High  
VIH  
VIL  
0.7 × VDDx  
V
V
Logic Low  
0.3 × VDDx  
Output Voltage  
Logic High  
2
VOH  
VOL  
II  
VDDx − 0.1  
VDDx − 0.4  
VDDx  
VDDx − 0.2  
0.0  
0.2  
+0.01  
V
V
V
V
IOx1 = −20 µA, VIx = VIxH  
2
IOx1 = −4 mA, VIx = VIxH  
IOx1 = 20 µA, VIx = VIxL  
3
Logic Low  
0.1  
0.4  
+10  
3
IOx1 = 4 mA, VIx = VIxL  
Input Current per Channel  
Quiescent Supply Current  
ADuM220N/ADuM225N  
−10  
µA  
0 V ≤ VIx ≤ VDDx  
IDD1 (Q)  
IDD2 (Q)  
IDD1 (Q)  
IDD2 (Q)  
0.9  
1.3  
6.4  
1.4  
1.3  
1.8  
10.0  
1.9  
mA  
mA  
mA  
mA  
VI4 = 0 (N0), 1 (N1)5  
VI4 = 0 (N0), 1 (N1)5  
VI4 = 1 (N0), 0 (N1)5  
VI4 = 1 (N0), 0 (N1)5  
ADuM221N/ADuM226N  
IDD1 (Q)  
IDD2 (Q)  
IDD1 (Q)  
IDD2 (Q)  
1.1  
1.1  
4.0  
4.9  
1.6  
1.5  
5.8  
6.4  
mA  
mA  
mA  
mA  
VI4 = 0 (N0), 1 (N1)5  
VI4 = 0 (N0), 1 (N1)5  
VI4 = 1 (N0), 0 (N1)5  
VI4 = 1 (N0), 0 (N1)5  
Dynamic Supply Current  
Dynamic Input  
Dynamic Output  
Undervoltage Lockout  
Positive VDDx Threshold  
Negative VDDx Threshold  
VDDx Hysteresis  
IDDI (D)  
0.01  
0.02  
mA/Mbps Inputs switching, 50% duty cycle  
mA/Mbps Inputs switching, 50% duty cycle  
IDDO (D)  
UVLO  
VDDxUV+  
VDDxUV−  
VDDxUVH  
1.6  
1.5  
0.1  
V
V
V
Rev. 0 | Page 3 of 23  
 
 
 
 
 
 
 

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