Data Sheet
ADuM2210/ADuM2211
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All minimum/maximum specifications
apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current, per Channel, Quiescent
IDDI (Q)
0.4
0.5
0.8
0.6
mA
mA
Output Supply Current, per Channel, Quiescent IDDO (Q)
ADuM2210, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
1.3
1.0
1.7
1.6
mA
mA
DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal
frequency
VDD2 Supply Current
IDD2 (Q)
10 Mbps (TR Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
3.5
1.7
4.6
2.8
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
ADuM2211, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
IDD2 (Q)
1.1
1.3
1.5
1.8
mA
mA
DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal
frequency
VDD2 Supply Current
10 Mbps (TR Grade Only)
VDD1 Supply Current
VDD2 Supply Current
For All Models
IDD1 (10)
IDD2 (10)
2.6
3.1
3.4
4.0
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
Input Currents
Logic High Input Threshold
IIA, IIB
VIH
−10
0.7 (VDD1
+0.01 +10
μA
V
0 V ≤ VIA, VIB ≤ VDD1 or VDD2
or VDD2
)
Logic Low Input Threshold
Logic High Output Voltages
VIL
0.3 (VDD1
or VDD2
V
V
)
VOAH
(VDD1 or
DD2) −
0.1
(VDD1 or
VDD2) −
0.5
5.0
4.8
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
V
VOBH
V
Logic Low Output Voltages
VOAL
VOBL
0.0
0.04
0.2
0.1
0.1
0.4
V
V
V
IOx = 20 μA, VIx = VIxL
IOx = 400 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM221xSR
Minimum Pulse Width2
Maximum Data Rate3
PW
1000
ns
Mbps
ns
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
20
Propagation Delay4
tPHL, tPLH
PWD
tPSK
tPSKCD/tPSKOD
tR/tF
150
40
100
50
4
Pulse Width Distortion, |tPLH − tPHL
|
Propagation Delay Skew5
Channel-to-Channel Matching6
ns
ns
Output Rise/Fall Time (10% to 90%)
10
Rev. A | Page 3 of 2