Data Sheet
ADuM160N/ADuM161N/ADuM162N/ADuM163N
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. Minimum/maximum specifications apply over the entire recommended
operation range of 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.
Table 1.
Parameter
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
SWITCHING SPECIFICATIONS
Pulse Width
PW
6.6
150
4.8
ns
Mbps
ns
ns
ps/°C
ns
Within pulse width distortion (PWD) limit
Within PWD limit
50% input to 50% output
Data Rate1
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Propagation Delay Skew
tPHL, tPLH
PWD
7.2
0.5
1.5
13
4.5
|tPLH − tPHL|
tPSK
6.1
Between any two units at the
same temperature, voltage, and load
Channel Matching
Codirectional
Opposing Direction
Jitter
tPSKCD
tPSKOD
0.5
0.5
490
70
4.0
4.5
ns
ns
ps p-p
ps rms
See the Jitter Measurement section
See the Jitter Measurement section
DC SPECIFICATIONS
Input Threshold Voltage
Logic High
VIH
VIL
0.7 ×
VDDx
V
V
Logic Low
0.3 ×
VDDx
Output Voltage
Logic High
3
VOH
VDDx − 0.1 VDDx
VDDx − 0.4 VDDx
0.2
V
V
IOx2 = −20 µA, VIx = VIxH
3
−
IOx2 = −4 mA, VIx = VIxH
4
Logic Low
VOL
II
0.0
0.2
0.1
0.4
+10
V
V
µA
IOx2 = 20 µA, VIx = VIxL
4
IOx2 = 4 mA, VIx = VIxL
Input Current per Channel
Quiescent Supply Current
ADuM160N
−10
+0.01
0 V ≤ VIx ≤ VDDx
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.3
3.3
19.3
3.5
3.5
4.52
30
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1)6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
4.82
ADuM161N
ADuM162N
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.5
3.2
16.0
7.2
3.8
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1)6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
4.22
24.8
11.2
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
2.8
3.0
14.1
10.5
4.0
4.2
22.5
16.7
mA
mA
mA
mA
VI5 = 0 (N0), 1 (N1)6
VI5 = 0 (N0), 1 (N1)6
VI5 = 1 (N0), 0 (N1)6
VI5 = 1 (N0), 0 (N1)6
Rev. 0 | Page 3 of 23