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ADUM1400WSRWZ55-RL PDF预览

ADUM1400WSRWZ55-RL

更新时间: 2024-01-08 16:08:52
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管接口集成电路
页数 文件大小 规格书
31页 623K
描述
Interface Circuit, CMOS, PDSO16

ADUM1400WSRWZ55-RL 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:SOIC-16Reach Compliance Code:compliant
风险等级:5.56接口集成电路类型:INTERFACE CIRCUIT
JESD-30 代码:R-PDSO-G16长度:10.3 mm
功能数量:4端子数量:16
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED座面最大高度:2.65 mm
最大供电电压:5.5 V最小供电电压:3 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

ADUM1400WSRWZ55-RL 数据手册

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Data Sheet  
ADuM1400/ADuM1401/ADuM1402  
Parameter  
Symbol  
Min  
Typ Max Unit  
Test Conditions  
5
Pulse Width Distortion, |tPLH − tPHL  
|
PWD  
40  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
Change vs. Temperature  
Propagation Delay Skew6  
Channel-to-Channel Matching7  
11  
ps/°C  
ns  
ns  
tPSK  
tPSKCD/tPSKOD  
50  
50  
ADuM1400BRW/ADuM1401BRW/ADuM1402BRW  
Minimum Pulse Width3  
PW  
100 ns  
Mbps  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
Maximum Data Rate4  
10  
20  
Propagation Delay5  
Pulse Width Distortion, |tPLH − tPHL  
tPHL, tPLH  
PWD  
32  
5
50  
3
5
|
ns  
Change vs. Temperature  
Propagation Delay Skew6  
Channel-to-Channel Matching, Codirectional  
Channels7  
ps/°C  
ns  
ns  
tPSK  
tPSKCD  
15  
3
Channel-to-Channel Matching, Opposing-  
Directional Channels7  
tPSKOD  
6
ns  
CL = 15 pF, CMOS signal levels  
ADuM1400CRW/ADuM1401CRW/ADuM1402CRW  
Minimum Pulse Width3  
PW  
8.3  
120  
27  
0.5  
3
11.1 ns  
Mbps  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
Maximum Data Rate4  
90  
18  
Propagation Delay5  
Pulse Width Distortion, |tPLH − tPHL  
tPHL, tPLH  
PWD  
32  
2
5
|
ns  
Change vs. Temperature  
Propagation Delay Skew6  
Channel-to-Channel Matching, Codirectional  
Channels7  
ps/°C  
ns  
ns  
tPSK  
tPSKCD  
10  
2
Channel-to-Channel Matching, Opposing-  
Directional Channels7  
tPSKOD  
5
ns  
CL = 15 pF, CMOS signal levels  
For All Models  
Output Disable Propagation Delay (High/Low  
to High Impedance)  
Output Enable Propagation Delay (High  
Impedance to High/Low)  
Output Rise/Fall Time (10% to 90%)  
Common-Mode Transient Immunity at Logic  
High Output8  
tPHZ, tPLH  
tPZH, tPZL  
6
6
8
8
ns  
ns  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
CL = 15 pF, CMOS signal levels  
VIx = VDD1 or VDD2, VCM = 1000 V,  
transient magnitude = 800 V  
VIx = 0 V, VCM = 1000 V,  
tR/tF  
|CMH|  
2.5  
35  
ns  
kV/µs  
25  
25  
Common-Mode Transient Immunity at Logic  
Low Output8  
|CML|  
35  
kV/µs  
transient magnitude = 800 V  
Refresh Rate  
fr  
1.2  
0.19  
0.05  
Mbps  
mA/Mbps  
mA/Mbps  
Input Dynamic Supply Current per Channel9  
IDDI (D)  
Output Dynamic Supply Current per Channel9 IDDO (D)  
1 All voltages are relative to their respective ground.  
2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load  
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.  
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through  
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.  
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.  
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.  
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is  
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.  
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load  
within the recommended operating conditions.  
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of  
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with  
inputs on opposing sides of the isolation barrier.  
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate  
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient  
magnitude is the range over which the common mode is slewed.  
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information  
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current  
for a given data rate.  
Rev. L | Page 5 of 31  

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